DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 09 Jul 2026 for application number 18/494,594. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant Arguments/Remarks, and Claims.
Claims 1-2, 4, 6-10, 12-14, 20-25 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding independent claim 1, Applicant contends that the prior art does not teach, “a conductive pattern for a first source select line…includes a metal material or a metal silicide material”; Examiner respectfully disagrees. Lee teaches:
a conductive pattern for a first source select line [first select gate layer 181; Fig. 5A-B, paras 0082-0085] and a conductive pattern for a second source select line [third select gate layer 189; Fig. 5A-B, paras 0082-0085];
wherein the conductive pattern for the first source select line [181], the conductive pattern for the second source select line [189], and the insulating pattern [151] are sequentially stacked in the vertical direction [181, 189, and 151 are sequentially stacked in the vertical direction];
wherein the conductive pattern for the first source select line [181] includes a doped semiconductor material [para 0082 discloses 181 may be silicon and that impurities diffuse into it, i.e. 181 is doped]; and
wherein the conductive pattern for the second source select line [189] includes a metal material or a metal silicide material [para 0085 discloses 189 may be metals or metal silicide, like titanium silicide].
Examiner notes that the order in which the conductive patterns are stacked is not specified in the current language of claim 1. As such, the prior art reasonably teaches the invention of claim 1.
Independent Claim 10 is rejected for similar reasons.
Regarding independent claim 20, Applicant’s arguments with respect to claim 20 have been considered but are moot because of new grounds of rejection necessitated by amendment; see the Rejection below for prior art mappings and explanations.
Dependent claims 2, 4, 6-9, 12-14, and 21-25 are rejected for these reasons and for reasons as expressed in the Rejection below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 6-10, 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. [hereinafter as Lee] (US 2021/0217769 A1).
In reference to claim 1, Lee teaches A semiconductor memory device comprising:
a first gate stacked body [GST1; see annotated Fig. 5A below] including a plurality of interlayer insulating layers [interlayer insulating layers IL; Fig. 5A, para 0075] and a plurality of conductive patterns [conductive patterns CP1 to CPn; Fig. 5A, para 0075] that are alternately stacked in a vertical direction [D1; Fig. 5A];
a second gate stacked body [GST2; see annotated Fig. 5A below] including a source select line [source select line SSL1/SSL2; Fig. 5A, para 0076] and an insulating pattern [source gate insulating pattern 151; Fig. 5A, para 0068] that are sequentially formed on the first gate stacked body [GST1]; and
a channel structure [channel structures CH1-4; Fig. 5A, para 0065] extending into the first gate stacked body [GST1] and the second gate stacked body [GST2] in the vertical direction [D1], and including a first end upwardly protruding higher [CH1-4 protrude higher than GST1] than the second gate stacked body [GST2];
wherein the source select line [SSL1/SSL2] includes a conductive pattern for a first source select line [first select gate layer 181; Fig. 5A-B, paras 0082-0085] and a conductive pattern for a second source select line [third select gate layer 189; Fig. 5A-B, paras 0082-0085];
wherein the conductive pattern for the first source select line [181], the conductive pattern for the second source select line [189], and the insulating pattern [151] are sequentially stacked in the vertical direction [181, 189, and 151 are sequentially stacked in the vertical direction];
wherein the conductive pattern for the first source select line [181] includes a doped semiconductor material [para 0082 discloses 181 may be silicon and that impurities diffuse into it, i.e. 181 is doped]; and
wherein the conductive pattern for the second source select line [189] includes a metal material or a metal silicide material [para 0085 discloses 189 may be metals or metal silicide, like titanium silicide].
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In reference to claim 2, Lee teaches The semiconductor memory device according to claim 1, wherein at least one of the plurality of conductive layers [181/187S/189] is a metal layer [187S may include tungsten, para 0083; 189 may include various metals, para 0085].
In reference to claim 4, Lee teaches The semiconductor memory device according to claim 1, wherein the conductive pattern for the second source select line [189] has a resistance value lower than [para 0083 discloses that 189 may be a material, i.e. titanium silicide, with a lower resistance value that 181, i.e. doped silicon] that of the conductive pattern for the first source select line [181].
In reference to claim 6, Lee teaches The semiconductor memory device according to claim 1, wherein the conductive pattern for the second source select line [189] is a titanium silicide layer [para 0085 discloses 189 may be titanium silicide].
In reference to claim 7, Lee teaches The semiconductor memory device according to claim 1, further comprising: a memory layer [memory layer ML; Fig. 5A, para 0065] enclosing a sidewall of the channel structure [CH1-4]; and a source line [common source line CSL; Fig. 5A, para 0059] formed on the second gate stacked body [GST2].
In reference to claim 8, Lee teaches The semiconductor memory device according to claim 7, wherein the channel structure [CH1-4] comprises: a core insulating layer [core insulating layer CO; Fig. 5A, para 0066] formed to extend in the vertical direction [D1] in a central region of the channel structure [CH1-4]; and a channel layer [channel layer CL; Fig. 5A, para 0066] enclosing a sidewall of the core insulating layer [CO].
In reference to claim 9, Lee teaches The semiconductor memory device according to claim 8, wherein the first end of the channel structure [CH1-4] extends into the source line [CSL], and the channel layer [CL] directly contacts the source line [CSL].
In reference to claim 10, Lee teaches A semiconductor memory device comprising: a
first gate stacked body [GST1; see annotated Fig. 5A above] including a plurality of interlayer insulating layers [interlayer insulating layers IL; Fig. 5A, para 0075] and a plurality of conductive patterns [conductive patterns CP1 to CPn; Fig. 5A, para 0075] that are alternately stacked in a vertical direction [D1; Fig. 5A];
a second gate stacked body [GST2; see annotated Fig. 5A above] including a source select line [source select line SSL1/SSL2; Fig. 5A, para 0076] and an insulating pattern [source gate insulating pattern 151; Fig. 5A, para 0068] that are sequentially formed on the first gate stacked body [GST1]; and
a channel structure [channel structures CH1-4; Fig. 5A, para 0065] extending into the first gate stacked body [GST1] and the second gate stacked body [GST2] in the vertical direction [D1], and including a first end upwardly protruding higher [CH1-4 protrude higher than GST1] than the second gate stacked body [GST2];
wherein the source select line [SSL1/SSL2] includes a conductive pattern for a first source select line [first select gate layer 181; Fig. 5A-B, paras 0082-0085] and a conductive pattern for a second source select line [third select gate layer 189; Fig. 5A-B, paras 0082-0085], the conductive pattern for the second source select line [189] formed on the conductive pattern for the first source select line [181], and
wherein the conductive pattern for the second source select line [189] is a metal layer [para 0085 discloses 189 may be metals or metal silicide, like titanium silicide];
wherein the conductive pattern for the first source select line [181] is a doped semiconductor layer [para 0082 discloses 181 may be silicon and that impurities diffuse into it, i.e. 181 is doped]; and
wherein the conductive pattern for the first source select line [181], the conductive pattern for the second source select line [189], and the insulating pattern [151] are sequentially stacked on the first gate stacked body [181, 189, and 151 are sequentially stacked in the vertical direction].
In reference to claim 12, Lee teaches The semiconductor memory device according to claim 10, wherein the conductive pattern for the second source select line [189] has a resistance value lower than [para 0083 discloses that 189 may be a material, i.e. titanium silicide, with a lower resistance value that 181, i.e. doped silicon] a resistance value of the conductive pattern for the first source select line [181].
In reference to claim 13, Lee teaches The semiconductor memory device according to claim 10, wherein the conductive pattern for the second source select line [189] is a titanium silicide layer [para 0085 discloses 189 may be titanium silicide].
In reference to claim 14, Lee teaches The semiconductor memory device according to claim 10, further comprising: a memory layer [memory layer ML; Fig. 5A, para 0065] enclosing a sidewall of the channel structure [CH1-4]; and a source line [source layer CSL; Fig. 5A, para 0059] formed on the second gate stacked body [GST2].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 20-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Liu et al. [hereinafter as Liu] (US 2021/0118989 A1) further in view of Lee [hereinafter as Lee2] (US 2022/0077182 A1).
In reference to claim 20, Lee teaches A semiconductor memory device comprising:
a first gate stacked body [GST1; see annotated Fig. 5A above] including a plurality of interlayer insulating layers [interlayer insulating layers IL; Fig. 5A, para 0075] and a plurality of conductive patterns [conductive patterns CP1 to CPn; Fig. 5A, para 0075] that are alternately stacked in a vertical direction [D1; Fig. 5A];
a second gate stacked body [GST2; see annotated Fig. 5A above] including a source select line [source select line SSL1/SSL2; Fig. 5A, para 0076] and an insulating pattern [source gate insulating pattern 151; Fig. 5A, para 0068] that are sequentially formed on the first gate stacked body [GST1];
a channel structure [channel structures CH1-4; Fig. 5A, para 0065] extending into the first gate stacked body [GST1] and the second gate stacked body [GST2] in the vertical direction [D1], and including a first end upwardly protruding higher [CH1-4 protrude higher than GST1] than the second gate stacked body [GST1]; and
a source line [common source line CSL; Fig. 5A, para 0059] connected to the channel structure [CH1-4];
wherein the source select line [SS1/SS2] includes a conductive pattern for a first source select line [first select gate layer 181; Fig. 5A-B, paras 0082-0085] and a conductive pattern for a second source select line [third select gate layer 189; Fig. 5A-B, paras 0082-0085];
wherein the conductive pattern for the first source select line [181 of SS1/1SS2] includes a first conductive material [181 is made of conductive material] and the conductive pattern for the second source select line [189 of SS1/SS2] includes a second conductive material [189 is made of conductive material]; and
wherein the second conductive material [189] having a resistance lower [para 0085 discloses that 189 may be titanium silicide; para 0082 discloses that 181 may be silicon; titanium silicide has a resistance lower than silicon] than the first conductive material [181].
However, Lee does not explicitly teach wherein the conductive pattern for the second source select line is disposed between the conductive pattern for the first source select line and the source line, that is, Lee does not explicitly teach the positions of these conductive patterns relative to one another.
Liu teaches in paragraph 0091 that select gates 332/334 may including conductor materials such as doped silicon, metals, and silicides, similar to the claimed invention. Therefore, Liu provides a teaching in which any one or a combination of these materials may be made and positioned in a semiconductor structure.
Lee and Lee2 explicitly teach wherein the conductive pattern for the second source select line [first metal barrier layer 183 of Lee2; Fig. 3A, para 0045] is disposed between [the combination of Lee and Lee2 would provide a metal layer 183 of Lee2 between the CSL and doped silicon 181 of Lee] the conductive pattern for the first source select line [181 of Lee] and the source line [CSL of Lee].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Lee, Liu, and Lee2 before the effective filing date of the claimed invention, to include the ordering of select line layers as disclosed by Liu and Lee2 into the semiconductor device of Lee in order to obtain a semiconductor device in which a metal select line is between a silicon select line and a common source line.
One of ordinary skill in the art would be motivated to obtain a semiconductor device in which a metal select line is between a silicon select line and a common source line to provide the predictable result of reducing electrical resistance and improving switching speeds.
In reference to claim 21, Lee, Liu, and Lee2 teach the invention of claim 20.
Lee teaches The semiconductor memory device according to claim 20, wherein the first conductive material [181] includes a doped semiconductor material [para 0082 discloses 181 may be silicon and that impurities diffuse into it].
In reference to claim 22, Lee, Liu, and Lee2 teach the invention of claim 21.
Lee teaches The semiconductor memory device according to claim 21, wherein the second conductive material [189] includes a titanium silicide [para 0085 discloses 189 may be titanium silicide].
In reference to claim 23, Lee, Liu, and Lee2 teach the invention of claim 20.
Lee teaches The semiconductor memory device according claim to 20, wherein the channel structure [CH1-4] penetrates the conductive pattern for the first source select line [181] and the conductive pattern for the second source select line [189].
In reference to claim 24, Lee, Liu, and Lee2 teach the invention of claim 20.
Lee teaches The semiconductor memory device according to claim 20, wherein the conductive pattern for the first source select line [181] and the conductive pattern for the second source select line [189] enclose the channel structure [CH1-4].
In reference to claim 25, Lee, Liu, and Lee2 teach the invention of claim 20.
Lee teaches The semiconductor memory device according to claim 20, wherein the second conductive material [189] having the resistance lower [para 0085 discloses that 189 may be titanium silicide; paras 0083-0084 disclose that CP1 to CPn may be tungsten; titanium silicide has resistance less than that of tungsten] than the plurality of conductive patterns [CP1 to CPn].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW CHUNG whose telephone number is (571)272-5237. The examiner can normally be reached M-F 9-5pm.
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/ANDREW CHUNG/
Examiner, Art Unit 2898
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