DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Applicant's election without traverse of claims 1-16 in the reply filed on 1/26/2026 is acknowledged.
3. Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-10, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2022/0223494) (hereafter Lee).
Regarding claim 1, Lee discloses a compound component device comprising:
a plurality of laminated first compound component layers (425 and lower portion of 421 excluding top 101 in Fig. 41B) housing first electronic components (159 and top 190 in Fig. 41B, paragraph 0157), wherein
the first compound component layers (425 and lower portion of 421 excluding top 101 in Fig. 41B) each include an electronic component layer (425 and lower portion of 421 excluding top 101 in Fig. 41B), including a first main surface (top surface of top 190 in Fig. 41B) and a second main surface (bottom surface of top 190 in Fig. 41B) opposed to the first main surface (top surface of top 190 in Fig. 41B), and a redistribution layer (top 101 and 34 contacting top 190 in Fig. 41B) on the first main surface (top surface of top 190 in Fig. 41B),
at least two of the plurality of first compound component layers (425 and lower portion of 421 excluding top 101 in Fig. 41B) configure an inverted layer 425 (Fig. 41B) for which the first compound component layers (425 and lower portion of 421 excluding top 101 in Fig. 41B) are paired and configured so that the second main surfaces (see Fig. 41B, wherein bottom surface of top 190 and top surface of 159 face each other) face each other,
the electronic component layer (lower portion of 421 excluding top 101 in Fig. 41B) includes the first electronic component (top 190 in Fig. 41B), a first resin sealing portion (92 of 421 in Fig. 41B, paragraph 0331) to seal the first electronic component (top 190 in Fig. 41B), a side wall portion (467 of 421 in Fig. 41B, paragraph 0116) that encloses the first electronic component (top 190 in Fig. 41B), and electronic component layer piercing vias (358 of 421 in Fig. 41B, paragraph 0373) that pierce the side wall portion (467 of 421 in Fig. 41B) and to electrically connect with the redistribution layer (top 101 and 34 contacting top 190 in Fig. 41B), and
the first electronic component (top 190 in Fig. 41B) is directly joined to the redistribution layer (top 101 and 34 contacting top 190 in Fig. 41B).
Regarding claim 2, Lee further discloses the compound component device according to Claim 1, wherein the redistribution layer (top 101 and 34 contacting top 190 in Fig. 41B) includes dielectric film 42 (Fig. 41B, paragraph 0103, wherein “silicone”) including inorganic material.
Regarding claim 3, Lee further discloses the compound component device according to Claim 1, wherein the side wall portion 467 (Fig. 41B) substantially includes silicon 257 (Fig. 41B, paragraph 0110, wherein “silicone”).
Regarding claim 6, Lee further discloses the compound component device according to Claim 1, further comprising: a second compound component layer (lower portion of 428 excluding bottom 101 in Fig. 41B), as an outermost layer, including a second electronic component (bottom 190 in Fig. 41B) and a second resin sealing portion (92 of 428 in Fig. 41B) to seal the second electronic component (bottom 190 in Fig. 41B).
Regarding claim 7, Lee further discloses the compound component device according to Claim 6, wherein the second compound component layer (lower portion of 428 excluding bottom 101 in Fig. 41B) is absent a side wall portion 467 (Fig. 41B).
Regarding claim 8, Lee (utilized different elements for first compound component layers, first electronic components, and an electronic component layer as applied in claim 1 in the above) discloses a compound component device comprising:
a plurality of laminated first compound component layers (425, layers below 425, and layers above 425 in Fig. 41B) housing first electronic components (159 and 190 in Fig. 41B, paragraph 0157), wherein
the first compound component layers (425, layers below 425, and layers above 425 in Fig. 41B) each include an electronic component layer (layers above 425 in Fig. 41B), including a first main surface (top surface of top 190 in Fig. 41B) and a second main surface (bottom surface of top 190 in Fig. 41B) opposed to the first main surface (top surface of top 190 in Fig. 41B), and a redistribution layer (top 101 and 34 contacting top 190 in Fig. 41B) on the first main surface (top surface of top 190 in Fig. 41B),
at least two of the plurality of first compound component layers (425, layers below 425, and layers above 425 in Fig. 41B) configure an inverted layer 425 (Fig. 41B) for which the first compound component layers (425, layers below 425, and layers above 425 in Fig. 41B) are paired and configured so that the second main surfaces (see Fig. 41B, wherein bottom surface of top 190 and top surface of 159 face each other) face each other,
the electronic component layer (layers above 425 in Fig. 41B) includes the first electronic component (top 190 in Fig. 41B), a first resin sealing portion (92 of 421 in Fig. 41B, paragraph 0331) to seal the first electronic component (top 190 in Fig. 41B), a side wall portion (467 of 421 in Fig. 41B, paragraph 0116) that encloses the first electronic component (top 190 in Fig. 41B), and electronic component layer piercing vias (358 of 421 in Fig. 41B, paragraph 0373) that pierce the side wall portion (467 of 421 in Fig. 41B) and to electrically connect with the redistribution layer (top 101 and 34 contacting top 190 in Fig. 41B),
the first electronic component (top 190 in Fig. 41B) is directly joined to the redistribution layer (top 101 and 34 contacting top 190 in Fig. 41B); and
wherein the inverted layer 425 (Fig. 41B) is in at least a center of the plurality of first compound component layers (425, layers below 425, and layers above 425 in Fig. 41B) with respect to a laminating direction (vertical direction in Fig. 41B), and the first compound component layer (425, layers below 425, and layers above 425 in Fig. 41B) that does not configure the inverted layer 425 (Fig. 41B) is an outermost layer of the compound component device.
Regarding claim 9, Lee further discloses the compound component device according to Claim 1, wherein the electronic component layer piercing vias (358 of 421 in Fig. 41B, paragraph 0373) are in zigzag configuration or configured in alignment in a section (horizontal section of 358 of 421 in Fig. 41B) perpendicular to a laminating direction (vertical direction in Fig. 41B) of the first compound component layers (425 and lower portion of 421 excluding top 101 in Fig. 41B).
Regarding claim 10, Lee further discloses the compound component device according to Claim 1, wherein the electronic component layer piercing vias (358 of 421 in Fig. 41B, paragraph 0373) are substantially parallel to a laminating direction (vertical direction in Fig. 41B) of the first compound component layers (425 and lower portion of 421 excluding top 101 in Fig. 41B), and the electronic component layer piercing vias (358 of 421 in Fig. 41B) are on one straight line in at least one pair of adjoining first compound component layers (425 and lower portion of 421 excluding top 101 in Fig. 41B) among the plurality of compound component layers.
Regarding claim 15, Lee further discloses the compound component device according to Claim 1, wherein the first electronic component (159 and top 190 in Fig. 41B) includes a first surface (top surface of 190 in Fig. 41B) on which component electrodes (34 contacting top 190 in Fig. 41B) are present and a second surface (bottom surface of 190 in Fig. 41B) opposed to the first surface (top surface of 190 in Fig. 41B), and the plurality of first compound component layers (425 and lower portion of 421 excluding top 101 in Fig. 41B) are joined together by a bonding layer 167 (Fig. 41B, paragraph 0381), and the second surface (top surface of 190 in Fig. 41B) of the first electronic component (159 and top 190 in Fig. 41B) is in contact with the bonding layer 167 (Fig. 41B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, and further in view of Elsherbini et al. (US 2019/0385977) (hereafter Elsherbini).
Regarding claim 4, Lee discloses the compound component device according to Claim 1, however Lee does not disclose the electronic component layer includes a plurality of first electronic components per layer.
Elsherbini discloses the electronic component layer (104-1 and 104-3 in Fig. 1A, paragraph 0024) includes a plurality of first electronic components (114-1, 114-4, 114-3, 114-6, and 114-5 in Fig. 1A, paragraph 0024) per layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form the electronic component layer includes a plurality of first electronic components per layer, as taught by Elsherbini, since reducing (Elsherbini, paragraph 0077) the total cost of manufacture, improving yield, and increasing design flexibility by allowing different dies 114 (Elsherbini, Fig. 1A, paragraph 0077) (e.g., dies 114 formed using different fabrication technologies) to be readily swapped to achieve different functionality.
Regarding claim 16, Lee discloses the compound component device according to Claim 1, however Lee does not disclose the electronic component layer includes a plurality of first electronic components per layer, and the plurality of first electronic components are different.
Elsherbini discloses the electronic component layer (104-1 and 104-3 in Fig. 1A, paragraph 0024) includes a plurality of first electronic components (114-1, 114-4, 114-3, 114-6, and 114-5 in Fig. 1A, paragraph 0024) per layer, and the plurality of first electronic components (104-1 and 104-3 in Fig. 1A, paragraph 0024) are different (see paragraph 0077).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form the electronic component layer includes a plurality of first electronic components per layer, and the plurality of first electronic components are different, as taught by Elsherbini, since reducing (Elsherbini, paragraph 0077) the total cost of manufacture, improving yield, and increasing design flexibility by allowing different dies 114 (Elsherbini, Fig. 1A, paragraph 0077) (e.g., dies 114 formed using different fabrication technologies) to be readily swapped to achieve different functionality.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, and further in view of Seidemann et al. (US 2019/0287904) (hereafter Seidemann).
Regarding claim 5, Lee discloses the compound component device according to Claim 1, however Lee does not disclose resins that configure the respective first resin sealing portions of a plurality of the electronic component layers are different.
Seidemann discloses resins (110 and 120 in Fig. 2, paragraph 0021) that configure the respective first resin sealing portions (110 and 120 in Fig. 2) of a plurality of the electronic component layers (lower portion of 200 and upper portion of 200 in Fig. 2) are different (see paragraph 0021, wherein “the capping material is a thermally cured resin of a different quality from the mass 110.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form resins that configure the respective first resin sealing portions of a plurality of the electronic component layers are different, as taught by Seidemann, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, and further in view of Zhai et al. (US 2017/0141088) (hereafter Zhai).
Regarding claim 11, Lee discloses the compound component device according to Claim 1, however Lee does not disclose a plurality of the inverted layers.
Zhai discloses a plurality of the inverted layers 142 (Fig. 11, paragraph 0040).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form a plurality of the inverted layers, as taught by Zhai, since the effect on total package height (z-height) (Zhai, paragraph 0033) can be mitigated with fan out using RDL, which can be fabricated with substantially less thickness than for traditional interposers and wire bonding.
Regarding claim 12, Lee in view of Zhai discloses the compound component device according to Claim 11, however Lee does not disclose two adjoining inverted layers among the plurality of inverted layers are joined together with a bonding layer interposed therebetween.
Zhai discloses two adjoining inverted layers 142 (Fig. 11, paragraph 0040) among the plurality of inverted layers are joined together with a bonding layer (148 and 152 in Fig. 11) interposed therebetween.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form two adjoining inverted layers among the plurality of inverted layers are joined together with a bonding layer interposed therebetween, as taught by Zhai, since the effect on total package height (z-height) (Zhai, paragraph 0033) can be mitigated with fan out using RDL, which can be fabricated with substantially less thickness than for traditional interposers and wire bonding.
Regarding claim 13, Lee further discloses the compound component device according to Claim 12, wherein the electronic component layer piercing vias (358 of 421 in Fig. 41B, paragraph 0373) include side wall portion piercing vias (358 of 421 in Fig. 41B, paragraph 0373) that pierce the side wall portion (467 of 421 in Fig. 41B).
Lee does not disclose inter-inverted layer conducting vias that pierce the bonding layer to make electrical connections between the inverted layers, and a cross-sectional area of the inter-inverted layer conducting via is larger than a cross-sectional area of the side wall portion piercing via in a section perpendicular to a laminating direction of the first compound component layers.
Zhai discloses inter-inverted layer conducting vias 140 (Fig. 11, paragraph 0044) that pierce the bonding layer (148 and 152 in Fig. 11) to make electrical connections between the inverted layers 142 (Fig. 11, paragraph 0040), and a cross-sectional area of the inter-inverted layer conducting via 140 (Fig. 11) is larger than a cross-sectional area of the side wall portion piercing via 120 (Fig. 11, paragraph 0035) in a section perpendicular to a laminating direction (vertical direction in Fig. 11) of the first compound component layers (125, 155, and 185 in Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form inter-inverted layer conducting vias that pierce the bonding layer to make electrical connections between the inverted layers, and a cross-sectional area of the inter-inverted layer conducting via is larger than a cross-sectional area of the side wall portion piercing via in a section perpendicular to a laminating direction of the first compound component layers, as taught by Zhai, since the effect on total package height (z-height) (Zhai, paragraph 0033) can be mitigated with fan out using RDL, which can be fabricated with substantially less thickness than for traditional interposers and wire bonding.
Regarding claim 14, Lee in view of Zhai discloses the compound component device according to Claim 11, however Lee does not disclose the plurality of first compound component layers configure an even number of inverted layers, and the even number of inverted layers are symmetrical with respect to a center in a laminating direction of the even number of inverted layers.
Zhai discloses the plurality of first compound component layers (125, 155, and 185 in Fig. 11) configure an even number of inverted layers 142 (Fig. 11, paragraph 0040), and the even number of inverted layers 142 (Fig. 11) are symmetrical with respect to a center in a laminating direction (vertical direction in Fig. 11) of the even number of inverted layers 142 (Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lee to form the plurality of first compound component layers configure an even number of inverted layers, and the even number of inverted layers are symmetrical with respect to a center in a laminating direction of the even number of inverted layers, as taught by Zhai, since the effect on total package height (z-height) (Zhai, paragraph 0033) can be mitigated with fan out using RDL, which can be fabricated with substantially less thickness than for traditional interposers and wire bonding.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813