DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of invention group I in the reply filed on 01/23/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Response to Amendment
Applicant’s amendment dated 01/23/2026, in which claims 9-13 were cancelled, has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application TW112137832 filed on 10/03/2023. The foreign application is not in English. The certified copy of the foreign priority application TW112137832 has been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application TW112137832 that is not in English, an English translation of the non-English language foreign application TW112137832 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature of “wherein in a cross-sectional view, a thickness of the spacer positioned on a right side of the RRAM device is different from a thickness of the spacer positioned on a left side of the RRAM device” of claim 5 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Wang et al. (US Pub. 20220209112).
Regarding claim 1, Wang et al. discloses in Fig. 8 a semiconductor device, comprising:
a resistive random access memory (RRAM) device [122, 124, 126 and V1];
a dual damascene structure disposed near the RRAM device [122, 124, 126 and V1]; and
a spacer [130] disposed in a sidewall of the RRAM device [122, 124, 126 and V1],
wherein the RRAM device [122, 124, 126 and V1] comprises:
a lower electrode [122];
a metal oxide layer [tantalum oxide 124a] disposed on the lower electrode [122]; and
an upper electrode [126 and V1] disposed on the metal oxide layer [tantalum oxide 124a];
the dual damascene structure comprises:
a via; and
a wire disposed on the via, wherein a top part of the wire is coplanar with a top part of the upper electrode [126 and V1] of the RRAM device.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al. (US Pub. 20170092693) in view of Yang (US Pub. 20220059762).
Regarding claims 1-2, 4, 6-8, Tan et al. discloses in Fig. 1b, paragraph [0013], [0040]-[0041], [0047] a semiconductor device, comprising:
a memory device [160];
a dual damascene structure [174 and 175] disposed near the memory device [160]; and
a spacer [182] disposed in a sidewall of the memory device [160],
wherein the memory device [160] comprises:
a lower electrode [162];
a memory layer [164] disposed on the lower electrode [162]; and
an upper electrode [166] disposed on the memory layer [164];
the dual damascene structure [174 and 175] comprises:
a via [174]; and
a wire [175] disposed on the via [174], wherein a top part of the wire [175] is coplanar with a top part of the upper electrode [166] of the memory device;
wherein a bottom surface of the lower electrode [162] is coplanar with a bottom part of the dual damascene structure [174 and 175];
wherein a material of the lower electrode [162] comprises titanium and a material of the upper electrode comprises titanium nitride [paragraph [0068], [0077]].
Tan et al. fails to disclose in Fig. 1b,
the memory device is a resistive random access memory (RRAM) device;
the memory layer is a metal oxide layer;
wherein a top part of the spacer is coplanar with the top part of the upper electrode of the RRAM device;
wherein in a cross-sectional view, a shape of the spacer is formed in a rectangle;
wherein the metal oxide layer is formed in a U-shape;
a material of the metal oxide layer comprises hafnium oxide.
However, Tan et al. discloses in paragraph [0013] and [0040] that “embodiments of the present disclosure are also applicable to other suitable types of memory element such as resistive random access memory (RRAM)” and “Other suitable types of storage elements or memory cells may also be useful.”
Yang discloses in Fig. 9, paragraph [0009], [0023], [0039]-0040]
the memory device is a resistive random access memory (RRAM) device;
the memory layer [RL1 or RL2] is a metal oxide layer [paragraph [0023]];
wherein a top part of the spacer [32A or 32B] is coplanar with the top part of the upper electrode [TE1 or TE2] of the RRAM device;
wherein in a cross-sectional view, a shape of the spacer [32A or 32B] is formed in a rectangle;
wherein the metal oxide layer [RL2] is formed in a U-shape [paragraph [0039]];
a material of the metal oxide layer [RL2] comprises hafnium oxide [paragraph [0023].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yang into the method of Tan et al. to include the memory device is a resistive random access memory (RRAM) device; the memory layer is a metal oxide layer; wherein a top part of the spacer is coplanar with the top part of the upper electrode of the RRAM device; wherein in a cross-sectional view, a shape of the spacer is formed in a rectangle; wherein the metal oxide layer is formed in a U-shape; a material of the metal oxide layer comprises hafnium oxide. The ordinary artisan would have been motivated to modify Tan et al. in the above manner for the purpose of suitable alternative configuration of memory element having the characteristics of low operating voltage, low power consumption, and high writing speed [paragraph [0013] of Tan et al. and paragraph [0002] of Yang].
Alternatively,
Regarding claims 1-2, 4, 6-8, Yang discloses in Fig. 9, paragraph [0009], [0023], [0039]-0040] a semiconductor device, comprising:
a resistive random access memory (RRAM) device;
a spacer [32A or 32B] disposed in a sidewall of the RRAM device, wherein the RRAM device comprises:
a lower electrode [BE1 or BE2];
a metal oxide layer [RL1 or RL2] disposed on the lower electrode [BE1 or BE2]; and
an upper electrode [TE1 or TE2] disposed on the metal oxide layer [RL1 or RL2];
wherein a top part of the spacer [32A or 32B] is coplanar with the top part of the upper electrode [TE1 or TE2] of the RRAM device;
wherein in a cross-sectional view, a shape of the spacer [32A or 32B] is formed in a rectangle;
wherein the metal oxide layer [RL2] is formed in a U-shape [paragraph [0039]];
a material of the metal oxide layer [RL1 or RL2] comprises hafnium oxide [paragraph [0023]].
Yang fails to disclose
a dual damascene structure disposed near the RRAM device;
the dual damascene structure comprises:
a via; and
a wire disposed on the via, wherein a top part of the wire is coplanar with a top part of the upper electrode of the RRAM device.
wherein a bottom surface of the lower electrode is coplanar with a bottom part of the dual damascene structure;
wherein a material of the lower electrode comprises titanium, and a material of the upper electrode comprises titanium nitride.
Tan et al. discloses in Fig. 1b, paragraph [0013], [0040]-[0041], [0047]
a dual damascene structure [174 and 175] disposed near the RRAM device [160][paragraph [0013] “embodiments of the present disclosure are also applicable to other suitable types of memory element such as resistive random access memory (RRAM)”]; and
the dual damascene structure [174 and 175] comprises:
a via [174]; and
a wire [175] disposed on the via [174], wherein a top part of the wire [175] is coplanar with a top part of the upper electrode [166] of the RRAM device;
wherein a bottom surface of the lower electrode [162] is coplanar with a bottom part of the dual damascene structure [174 and 175];
wherein a material of the lower electrode [162] comprises titanium and a material of the upper electrode comprises titanium nitride [paragraph [0068], [0077]].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Tan et al. into the method of Yang to include a dual damascene structure disposed near the RRAM device;
the dual damascene structure comprises: a via; and a wire disposed on the via, wherein a top part of the wire is coplanar with a top part of the upper electrode of the RRAM device; wherein a bottom surface of the lower electrode is coplanar with a bottom part of the dual damascene structure; wherein a material of the lower electrode comprises titanium, and a material of the upper electrode comprises titanium nitride. The ordinary artisan would have been motivated to modify Yang in the above manner for the purpose of integrating of the RRAM device with logic device into a single chip or an integrated circuit (IC) to form an embedded memory in a reliable, simplified and cost effective way [paragraph [0002], [0013], [0101] of Tan et al.].
Regarding claim 3, Tan et al. discloses in Fig. 1b,
the top part of the upper electrode [166] is coplanar with the top part of the wire [175].
Yang discloses in Fig. 9
a top part of the spacer [32A or 32B] is coplanar with the top part of the upper electrode [TE1 or TE2].
Thus, the combination of Tan et al. and Yang would result to “wherein a top part of the spacer is coplanar with the top part of the wire”.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tan et al. (US Pub. 20170092693) in view of Yang (US Pub. 20220059762) as applied to claim 1 above and further in view of Chiu et al. (US Pub. 20210111339).
Regarding claim 5, Tan et al. and Yang fails to disclose
wherein in a cross-sectional view, a thickness of the spacer positioned on a right side of the RRAM device is different from a thickness of the spacer positioned on a left side of the RRAM device.
Chiu et al. discloses in Fig. 6A, paragraph [0055]
wherein in a cross-sectional view, a thickness [604] of the spacer positioned on a right side of the RRAM device [112] is different from a thickness [602] of the spacer positioned on a left side of the RRAM device [112][“the first width 602 may be less than the second width 604”].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chiu et al. into the method of Tan et al. and Yang to include wherein in a cross-sectional view, a thickness of the spacer positioned on a right side of the RRAM device is different from a thickness of the spacer positioned on a left side of the RRAM device. The ordinary artisan would have been motivated to modify Tan et al. and Yang in the above manner for the purpose of providing suitable widths of the spacer [paragraph [0055] of Chiu et al.].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893