DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 05/07/2026, in which claims 1-2, 7 were amended, claims 3, 5, 9-13 were cancelled, claims 14-23 were added, has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application TW112137832 filed on 10/03/2023. The foreign application is not in English. The certified copy of the foreign priority application TW112137832, an English translation of the non-English language foreign application TW112137832 with a statement that the translation is accurate in accordance with 37 CFR 1.55 have been received.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 7-8, 14-23 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Glassman et al. (US Pub. 20200144496).
Regarding claims 1-2, 4, 7, Glassman et al. discloses in Fig. 6B, paragraph [0028], [0031]-[0034], [0074]-[0080] a semiconductor device, comprising:
a resistive random access memory (RRAM) device [120];
a first dual damascene structure [4560 and 4540] disposed near the RRAM device [120]; and
a spacer [340] disposed in a sidewall of the RRAM device [120], wherein
the RRAM device [120] comprises:
a lower electrode [122 and 4240];
a metal oxide layer [126] disposed on the lower electrode [122 and 4240]; and
an upper electrode [132 and 4340] disposed on the metal oxide layer [126];
the first dual damascene structure [4560 and 4540] comprises:
a via [4560 and portion of barrier layer][See annotated drawing]; and
a wire [4540 or 4560 and portion of barrier layer] disposed on the via [4560], wherein a top part of the wire [4540] is coplanar with a top part of the upper electrode [132 and 4340] of the RRAM device, and
a top part of the spacer [340] is coplanar with the top part of the wire [4540];
wherein the top part of the spacer [340] is coplanar with the top part of the upper electrode [132 and 4340] of the RRAM device;
wherein in a cross-sectional view, a shape of the spacer [340] is formed in a rectangle;
wherein a bottom surface [bottom surface of 4240] of the lower electrode [122 and 4240] is coplanar with a bottom part of the first dual damascene structure.
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Regarding claim 8, Glassman et al. discloses in paragraph [0032]-[0033], [0079] wherein a material of the lower electrode [122 and 4240] comprises titanium, a material of the metal oxide layer [126] comprises hafnium oxide, and a material of the upper electrode [132 and 4340] comprises titanium nitride.
Regarding claims 14-15, Glassman et al. discloses in Fig. 3A, Fig. 6B, paragraph [0047], [0050]
a barrier layer [312] disposed between a dielectric layer [304 or 4120] and a metal layer [314 or 4080] underlying the RRAM device [120];
wherein a material of the barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or a stack thereof [tantalum nitride, Ta or TaN layers].
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Regarding claims 16-17, Glassman et al. discloses in Fig. 3A, Fig. 6B, paragraph [0047], [0050]
a barrier layer disposed between the first dual damascene structure and a dielectric layer in which the first dual damascene structure is formed;
wherein a material of the barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or a stack thereof.
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Regarding claims 18-19, 20-21, Glassman et al. discloses in Fig. 6B, paragraph [0049], [0076]-[0077], [0080]
a cover layer [etch stop layer 4220] disposed on a dielectric layer [4120] underlying the RRAM device [120] and the first dual damascene structure.
wherein a material of the cover layer [etch stop layer] comprises silicon nitride, silicon oxynitride, silicon nitride carbide, or nitrogen doped carbon [silicon nitride].
a cover layer [etch stop layer 4360] disposed on a dielectric layer [4200] in which the RRAM device [120] and the first dual damascene structure are formed;
wherein a material of the cover layer [etch stop layer] comprises silicon nitride, silicon oxynitride, silicon nitride carbide, or nitrogen doped carbon.
Regarding claims 22-23, Glassman et al. discloses in Fig. 6B, paragraph [0049], [0076]-[0077], [0080]
a dielectric layer [4420] over the RRAM device [120] and the first dual damascene structure, and a second dual damascene structure [4400 and 4380] formed in the dielectric layer [4420] and electrically connected to the upper electrode [132 and 4340];
a third dual damascene structure [4580 and 4600] formed in the dielectric layer [4420] and electrically connected to the first dual damascene structure disposed near the RRAM device [120].
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al. (US Pub. 20170092693) in view of Yang (US Pub. 20220059762).
Regarding claims 1-2, 4, 6-8, Tan et al. discloses in Fig. 1b, paragraph [0013], [0040]-[0041], [0047] a semiconductor device, comprising:
a memory device [160];
a dual damascene structure [174 and 175] disposed near the memory device [160]; and
a spacer [182] disposed in a sidewall of the memory device [160],
wherein the memory device [160] comprises:
a lower electrode [162];
a memory layer [164] disposed on the lower electrode [162]; and
an upper electrode [166] disposed on the memory layer [164];
the dual damascene structure [174 and 175] comprises:
a via [174]; and
a wire [175] disposed on the via [174], wherein a top part of the wire [175] is coplanar with a top part of the upper electrode [166] of the memory device;
wherein a bottom surface of the lower electrode [162] is coplanar with a bottom part of the dual damascene structure [174 and 175];
wherein a material of the lower electrode [162] comprises titanium and a material of the upper electrode comprises titanium nitride [paragraph [0068], [0077]].
Tan et al. fails to disclose in Fig. 1b,
the memory device is a resistive random access memory (RRAM) device;
the memory layer is a metal oxide layer;
wherein a top part of the spacer is coplanar with the top part of the upper electrode of the RRAM device;
wherein a top part of the spacer is coplanar with the top part of the wire;
wherein in a cross-sectional view, a shape of the spacer is formed in a rectangle;
wherein the metal oxide layer is formed in a U-shape;
a material of the metal oxide layer comprises hafnium oxide.
However, Tan et al. discloses in paragraph [0013] and [0040] that “embodiments of the present disclosure are also applicable to other suitable types of memory element such as resistive random access memory (RRAM)” and “Other suitable types of storage elements or memory cells may also be useful.”
Yang discloses in Fig. 9, paragraph [0009], [0023], [0039]-0040]
the memory device is a resistive random access memory (RRAM) device;
the memory layer [RL1 or RL2] is a metal oxide layer [paragraph [0023]];
wherein a top part of the spacer [32A or 32B] is coplanar with the top part of the upper electrode [TE1 or TE2] of the RRAM device;
wherein in a cross-sectional view, a shape of the spacer [32A or 32B] is formed in a rectangle;
wherein the metal oxide layer [RL2] is formed in a U-shape [paragraph [0039]];
a material of the metal oxide layer [RL2] comprises hafnium oxide [paragraph [0023].
Tan et al. discloses in Fig. 1b, the top part of the upper electrode [166] is coplanar with the top part of the wire [175].
Yang discloses in Fig. 9 a top part of the spacer [32A or 32B] is coplanar with the top part of the upper electrode [TE1 or TE2].
Thus, the combination of Tan et al. and Yang would result to “wherein a top part of the spacer is coplanar with the top part of the wire”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yang into the method of Tan et al. to include the memory device is a resistive random access memory (RRAM) device; the memory layer is a metal oxide layer; wherein a top part of the spacer is coplanar with the top part of the upper electrode of the RRAM device; wherein a top part of the spacer is coplanar with the top part of the wire; wherein in a cross-sectional view, a shape of the spacer is formed in a rectangle; wherein the metal oxide layer is formed in a U-shape; a material of the metal oxide layer comprises hafnium oxide. The ordinary artisan would have been motivated to modify Tan et al. in the above manner for the purpose of suitable alternative configuration of memory element having the characteristics of low operating voltage, low power consumption, and high writing speed [paragraph [0013] of Tan et al. and paragraph [0002] of Yang].
Alternatively,
Regarding claims 1-2, 4, 6-8, Yang discloses in Fig. 9, paragraph [0009], [0023], [0039]-0040] a semiconductor device, comprising:
a resistive random access memory (RRAM) device;
a spacer [32A or 32B] disposed in a sidewall of the RRAM device, wherein the RRAM device comprises:
a lower electrode [BE1 or BE2];
a metal oxide layer [RL1 or RL2] disposed on the lower electrode [BE1 or BE2]; and
an upper electrode [TE1 or TE2] disposed on the metal oxide layer [RL1 or RL2];
wherein a top part of the spacer [32A or 32B] is coplanar with the top part of the upper electrode [TE1 or TE2] of the RRAM device;
wherein in a cross-sectional view, a shape of the spacer [32A or 32B] is formed in a rectangle;
wherein the metal oxide layer [RL2] is formed in a U-shape [paragraph [0039]];
a material of the metal oxide layer [RL1 or RL2] comprises hafnium oxide [paragraph [0023]].
Yang fails to disclose
a dual damascene structure disposed near the RRAM device;
the dual damascene structure comprises:
a via; and
a wire disposed on the via, wherein a top part of the wire is coplanar with a top part of the upper electrode of the RRAM device;
wherein a top part of the spacer is coplanar with the top part of the wire
wherein a bottom surface of the lower electrode is coplanar with a bottom part of the dual damascene structure;
wherein a material of the lower electrode comprises titanium, and a material of the upper electrode comprises titanium nitride.
Tan et al. discloses in Fig. 1b, paragraph [0013], [0040]-[0041], [0047]
a dual damascene structure [174 and 175] disposed near the RRAM device [160][paragraph [0013] “embodiments of the present disclosure are also applicable to other suitable types of memory element such as resistive random access memory (RRAM)”]; and
the dual damascene structure [174 and 175] comprises:
a via [174]; and
a wire [175] disposed on the via [174], wherein a top part of the wire [175] is coplanar with a top part of the upper electrode [166] of the RRAM device;
wherein a bottom surface of the lower electrode [162] is coplanar with a bottom part of the dual damascene structure [174 and 175];
wherein a material of the lower electrode [162] comprises titanium and a material of the upper electrode comprises titanium nitride [paragraph [0068], [0077]].
Tan et al. discloses in Fig. 1b, the top part of the upper electrode [166] is coplanar with the top part of the wire [175].
Yang discloses in Fig. 9 a top part of the spacer [32A or 32B] is coplanar with the top part of the upper electrode [TE1 or TE2].
Thus, the combination of Tan et al. and Yang would result to “wherein a top part of the spacer is coplanar with the top part of the wire”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Tan et al. into the method of Yang to include a dual damascene structure disposed near the RRAM device;
the dual damascene structure comprises: a via; and a wire disposed on the via, wherein a top part of the wire is coplanar with a top part of the upper electrode of the RRAM device; wherein a top part of the spacer is coplanar with the top part of the wire; wherein a bottom surface of the lower electrode is coplanar with a bottom part of the dual damascene structure; wherein a material of the lower electrode comprises titanium, and a material of the upper electrode comprises titanium nitride. The ordinary artisan would have been motivated to modify Yang in the above manner for the purpose of integrating of the RRAM device with logic device into a single chip or an integrated circuit (IC) to form an embedded memory in a reliable, simplified and cost effective way [paragraph [0002], [0013], [0101] of Tan et al.].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Glassman et al. (US Pub. 20200144496) as applied to claim 1 above and in view of Yang (US Pub. 20220059762).
Regarding claim 6, Glassman et al. fails to disclose
wherein the metal oxide layer is formed in a U-shape.
Yang discloses in Fig. 9 and paragraph [0023], [0039]
wherein the metal oxide layer [RL2] is formed in a U-shape.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yang into the method of Glassman et al. to include wherein the metal oxide layer is formed in a U-shape. The ordinary artisan would have been motivated to modify Glassman et al. in the above manner for the purpose of providing suitable alternative configuration of the metal oxide layer [paragraph [0039] of Yang].
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 4, 6-8, 14-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In addition, Applicant's arguments filed 05/07/2026 have been fully considered but they are not persuasive. As previously stated in rejection of claim 3 and restated above, Tan et al. discloses in Fig. 1b, the top part of the upper electrode [166] is coplanar with the top part of the wire [175]. Yang discloses in Fig. 9 a top part of the spacer [32A or 32B] is coplanar with the top part of the upper electrode [TE1 or TE2]. Thus, the combination of Tan et al. and Yang would result to “wherein a top part of the spacer is coplanar with the top part of the wire”.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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