DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Foreign Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 12/08/2023.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/26/2023 and 06/17/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2,9,11-13 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. (PG Pub 2020/0381563; hereinafter Jang).
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Regarding claim 1, refer to the Examiner’s mark-up of Fig. 2 provided above, Jang teaches a semiconductor device (see claim limitations below) comprising:
first channel patterns 140 adjacent to each other (see Fig. 2);
a first gate electrode 160 that overlaps with one of the first channel patterns (see Fig. 2);
first source/drain patterns 150 between the first channel patterns (see Fig. 2); and
a first active contact 180 in contact with a side surface of each of the first source/drain patterns (see Fig. 2), wherein a crystal plane of the side surface of each of the first source/drain patterns is one of {100} planes (para [0074]).
Regarding claim 2, refer to the Examiner’s mark-up of Fig. 2 provided above, Jang teaches the side surface of each of the first source/drain patterns 150 is substantially planar (see Fig. 2).
Regarding claim 9, refer to the Examiner’s mark-up of Fig. 2 provided above, Jang teaches the side surface of each of the first source/drain patterns 150 is inclined (the sides abutting 180) (see Fig. 2).
Regarding claim 11, refer to the Examiner’s mark-up of Fig. 2 provided above, Jang teaches a semiconductor device (see claim limitations below) comprising:
first channel patterns 141,142,143 adjacent to each other (see Fig. 2);
a first gate electrode 160 that overlaps with one of the first channel patterns (see Fig. 2);
first source/drain patterns 150 between the first channel patterns (see Fig. 2); and
a first active contact 180 in contact with a side surface of each of the first source/drain patterns (see Fig. 2),
wherein the side surface of each of the first source/drain patterns is substantially planar (see Fig. 2),
wherein the first active contact comprises a first portion (bottom) in contact with respective bottom surfaces of the first source/drain patterns and a second portion (180 sidewalls in contact with the side surface of each of the first source/drain patterns (see Fig. 2), and
wherein a width of the second portion of the first active contact decreases as a distance to a top surface of the first portion of the first active contact decreases (see Fig. 2).
Regarding claim 12, refer to the Examiner’s mark-up of Fig. 2 provided above, Jang teaches a crystal plane of the side surface of each of the first source/drain patterns 150 is one of {100} planes (para [0074]).
Regarding claim 13, refer to the Examiner’s mark-up of Fig. 2 provided above, Jang teaches a side surface of the second portion of the first active contact is substantially planar (portion of 150 below 180) (see Fig. 2).
Regarding claim 18, refer to the Examiner’s mark-up of Fig. 2 provided above, Jang teaches a second active contact 180 (to the right of center 180) in contact with respective top surfaces of the first source/drain patterns 150 (see Fig. 2), wherein a width of the second active contact decreases as a distance to a top surface of the second portion of the first active contact decreases (see Fig. 2).
Regarding claim 19, refer to the Examiner’s mark-up of Fig. 2 provided above, Jang teaches each of the first channel patterns 141,142,143 comprises semiconductor patterns that overlap with each other (see Fig. 2).
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Regarding claim 20, refer to the Examiner’s mark-up of Fig. 2 provided above, Jang teaches a semiconductor device (see claim limitations below) comprising:
first channel patterns 141,142,143 (left and right columns) adjacent to each other (see Fig. 2);
a first gate electrode 160 that overlaps with one of the first channel patterns (see Fig. 2);
first source/drain patterns 150 between the first channel patterns (see Fig. 2); and
a first active contact 180 in contact with the first source/drain patterns (see Fig. 2), wherein the first active contact comprises a first portion (“por-1”) and a second portion (“por-2”),
wherein the second portion of the first active contact is between the first source/drain patterns and is on the first portion of the first active contact (see Fig. 2),
wherein each of the first channel patterns comprises semiconductor patterns that overlap with each other (see Fig. 2), wherein a crystal plane of a side surface of each of the semiconductor patterns is one of {100} planes (para [0074]),
wherein the first source/drain patterns each include a side surface in contact with the second portion of the first active contact, and wherein a crystal plane of the side surface of each of the first source/drain patterns is the one of the {100} planes (see Fig. 2).
Prior Art
2. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
a. Kim et al. (PG Pub 2022/0045103) teaches a semiconductor device.
b. Kang et al. (PG Pub 2023/0049858) teaches a semiconductor device.
Allowable Subject Matter
3. Claims 3-8, 10 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 3, the first active contact comprises: a first portion in contact with respective bottom surfaces of the first source/drain patterns; and a second portion in contact with the side surface of each of the first source/drain patterns. Claims 4-8 would be allowable, because they depend on allowable claim 3.
Claim 10 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 10, second channel patterns adjacent to each other; a second gate electrode that overlaps with one of the second channel patterns; and a second source/drain pattern between the second channel patterns, wherein the first channel patterns are on the second channel patterns, and wherein the first active contact is in contact with the second source/drain pattern.
Claim 14 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 14, second channel patterns adjacent to each other; a second gate electrode that overlaps with one of the second channel patterns; and a second source/drain pattern between the second channel patterns, wherein the first channel patterns are on the second channel patterns, and wherein the first portion of the first active contact is in contact with the second source/drain pattern. Claims 15-16 would be allowable, because they depend on allowable claim 14.
Claim 17 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 17, a power delivery conductive layer in contact with a bottom surface of the first portion of the first active contact.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817