DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-13, and 15-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200258688 A1 (Berolini) further in view of US 20230307389 A1 (Kuo).
Re claims 1, 4, 5 and 6, Berolini teaches a microelectronic assembly comprising:
a semiconductor structure (processor 400);
an interposer (integrate circuit package 402) electrically connected to the semiconductor structure;
a decoupling capacitor (capacitor 408) having a first surface (top surface 235) and an opposing second surface (bottom surface 245), wherein the decoupling capacitor contains alternating dielectric layers (alternating dielectric layers [0070]) and internal electrode layers, the internal electrode layers containing first internal electrode layers (internal electrode layers 205 and conductive via 225) and second internal electrode layers (internal electrode layers 215 conductive via 285), wherein the capacitor further contains a first external terminal (external terminals 32 connected to conductive via 225) that is electrically connected to the first internal electrode layers and disposed on the first surface of the capacitor, a second external terminal (external terminals 34 connected to conductive via 285) that is electrically connected to the first internal electrode layers and disposed on the second surface of the capacitor ([0070]),
a third external terminal (shield electrodes 275 connected to 215 in region 255) that is electrically connected to the second internal electrode layers and disposed on the first surface of the capacitor, and
a fourth external terminal (shield electrodes 275 connected to 215 in region 265) that is electrically connected to the second internal electrode layers and disposed on the second surface of the capacitor, wherein the first external terminal and the third external terminal are electrically connected to the wiring board below; and
a circuit board (circuit board 406), wherein the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the circuit board ([0018] Figs. 1A-2).
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Berolini does not explicitly teach an additional mount with feed through vias connecting the interposer to the circuit board (claim 1) nor wherein the assembly contains multiple semiconductor structures (claim 4) nor wherein the semiconductor structures are arranged in an array (claim 5) nor wherein the semiconductor structures are stacked (claim 6).
Kuo teaches a semiconductor structure (SoIC die stack 104 and adjacent chips 106a-106d) wherein the assembly contains multiple semiconductor structures (claim 4) wherein the semiconductor structures are arranged in an array (claim 5) wherein the semiconductor structures are stacked (claim 6);
an interposer (interposer 102) electrically connected to the semiconductor structure;
a package substrate (package substrate 101) electrically connected to the interposer;
a capacitor (capacitor in region 120) in the package assembly connected to the routing mounts;
a circuit board (PCB [0028] Fig. 1).
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It would have been obvious to one of ordinary skill in the art at the time of filing to add the additional package substrate between the PCB and the interposer of Berolini.
The motivation to do so is that each mount further expands the pitch of the connectors thereby allowing flip chip bonding of multiple die with finer die to be mounted to the interposer which then can have an increased pitch when connecting to the package substrate before being bonded on PCBs having larger bond site pitches.
Furthermore, the courts have found that mere duplication of parts has no patentable significance unless a new and unexpected result is produced (MPEP 2144.04 (VI)(B)).
Re claim 2, Berolini teaches wherein the semiconductor structure is an integrated circuit device (processor 400).
Re claim 3, Berolini teaches wherein the integrated circuit device includes a memory device, logic device, processor device, or a combination thereof ([0019]).
Re claim 7, Berolini teaches wherein the semiconductor structure is electrically connected to the interposer via one or more coupling components (ball grid array 412 [0019]).
Re claim 8, Berolini is silent with regards to the acceptable materials for the interposer 402 however Kuo teaches wherein the interposer includes an insulating material (dielectric layers [0029]) through which one or more conductive pathways (vertical and horizontal interconnect features [0029]) are formed, wherein the conductive pathways are in electrical connection with the coupling components (Fig. 1).
Re claim 9, Berolini is silent with regards to the acceptable materials for the interposer 402 however Kuo teaches wherein the insulating material includes an organic material, inorganic material, semiconductor material, or a combination thereof (dielectric is at the very least either organic or inorganic).
Re claim 10, Berolini is silent with regards to any detail of the interposer 402 however Kuo teaches wherein an electronic component is embedded within the interposer (structures to route and distribute power signals [0029]).
Re claim 7, Berolini is silent with regards to any detail of the interposer 402 however Kuo teaches wherein the electronic component includes a capacitor, resistor, inductor, fuse, diode, transformer, sensor, electrostatic discharge device, memory device, radio frequency device, power amplifier, power management device, antenna, microelectromechanical system, or a combination thereof (all routing lines are inherently resistors).
Re claim 12, Berolini and Kuo teach wherein the interposer is electrically connected to the package substrate via one or more coupling components (ball grid array 404).
Re claim 13, Berolini and Kuo teach wherein the package substrate includes an insulating material through which one or more conductive pathways are formed, wherein the conductive pathways are in electrical connection with the coupling components (see metal lines depicted through package substrate 101 which are embedded in dielectric Fig. 1).
Re claim 15, Berolini teaches wherein the first and second external terminals have a positive polarity, and the third and fourth external terminals have a negative polarity ([0054-0056]).
Re claim 16, Berolini teaches wherein at least one of the first, second, third, or fourth external terminals extend to an end surface of the capacitor (extend to the top and bottom end surfaces Fig. 1B).
Re claim 17, Berolini teaches wherein the first, second, third, and fourth external terminals do not extend to an end surface of the capacitor (do not extend to the sidewall edges Figs. 1B).
Re claim 18, Berolini teaches wherein the decoupling capacitor contains only the first external terminal and the third external terminal on the first surface, and only the second external terminal and the fourth external terminal on the second surface (Fig. 1B [0070]).
Re claim 19, Berolini teaches wherein the capacitor contains at least four external terminals on the first surface and at least four external terminals on the second surface (Fig. 1A, 1D-).
Re claim 20, Berolini teaches wherein the external terminals are arranged in a linear fashion on the first surface and the second surface (Fig. 1A-1B, 1D).
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Re claim 21, Berolini teaches wherein the external terminals are arranged in a multi-dimensional array on the first surface and the second surface (Fig. 1A-1B).
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Re claim 22, Berolini teaches wherein the first and the second internal electrode layers are arranged vertically (conductive via portions 225 and 285 are vertically arranged Fig. 1B).
Re claim 23, Berolini teaches wherein the first internal electrode layers contain lead tabs extending to the first surface for contact with the first external terminal and lead tabs extending to the second surface for contact with the third external terminal, and further wherein the second internal electrode layers contain lead tabs extending to the first surface for contact with the second external terminal and lead tabs extending to the second surface for contact with the fourth external terminal (conductive via portions 225/285 Fig. 1B).
Re claim 24, Berolini teaches wherein the first and the second internal electrode layers are arranged horizontally (Figs. 1B-1C)
Re claim 25, Berolini teaches wherein the first and the second internal electrode layers are connected to the first, second, third, and fourth external terminals through conductive vias (Fig. 1B).
Re claim 26, Berolini teaches wherein the dielectric layers of the decoupling capacitor include a ceramic material ([0079-0080]).
Re claim 27, Berolini teaches wherein the ceramic material is a barium titanate ceramic material ([0080]).
Re claim 28, Berolini teaches wherein the first, second, third, and fourth external terminals contain at least one plated layer ([0082-0083]).
Re claim 29, Berolini teaches wherein the plated layer is formed by a process that includes electroless plating, electrolytic plating, or a combination thereof ([0083]).
Re claim 30, Berolini and Kuo teach wherein the circuit board (PCB) is electrically connected to the package substrate (package substrate 101) via coupling components (BGA 128).
Re claim 31, Berolini and Kuo teach wherein the coupling components include solder (soldering techniques [0018]).
Re claim 32, Berolini and Kuo teach wherein the first and the third external terminals of the decoupling capacitor are electrically connected to the package substrate via coupling components (capacitor is connected to the mount below using BGA Fig. 2 Berolini).
Re claim 33, Berolini teaches wherein the second and the fourth external terminals of the decoupling capacitor are electrically connected to the circuit board via coupling components (ball grid array 404 Fig. 2).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200258688 A1 (Berolini) further in view of US 20230307389 A1 (Kuo) further in view of US 20140128247 A1 (Marin).
Re claim 14, Berolini and Kuo teach the microelectronic assembly of claim 13, howere both Berolini and Kuo are silent with regards to acceptable materials of the dielectric in the package substrate.
Marin teaches using silicon, glass, ceramic, or organic dielectrics for the build up layers of package substrates [0082].
It would have been obvious to one of ordinary skill in the art at the time of filing to form the package substrate of the combined invention of Berolini and Kuo o organic dielectric material.
The motivation to do so is that Berolini and Kuo are completely silent with regards to any material requirements for the package substrate therefore the ordinary skilled artisan would have to look to Marin to deduce what kinds of dielectric materials can be used to form a package substrate.
Applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896