DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 26 Oct 2023 for application number 18/494,808. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-34 are presented for examination. Elected claims 1-5, 7-9, 12-17, 19, 23-24, and 26-34 are examined below. Non-elected claims 6, 10-11, 18, 20-22, and 25 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 28 Jan 2025, 17 Sep 2025, 15 Jan 2026, 20 Feb 2026, and 31 Mar 2026 were filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of claims 1-9, 12-17, 19, 23-24, and 26-34, drawn to Device embodiment I, Modification A. in the reply filed on 11 Mar 2026 is acknowledged.
Claims 10-11, 18, 20-22, and 25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected embodiments, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11 Mar 2026.
Further, regarding claim 6, the claimed “stacked” semiconductor structures are not present in the elected embodiment of Fig. 1. Accordingly, claim 6 is withdrawn from consideration as being directed to a non-elected invention.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 7-9, 12-17, 19, 23-24, and 26-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. [hereinafter as Yang] (US 2023/0144129) in view of Berolini et al. [hereinafter as Berolini] (US 2020/0258688 A1).
In reference to claim 1, Yang teaches A microelectronic assembly comprising:
a semiconductor structure [first die D10/first interface D11; Fig. 2, para 0013];
an interposer [interposer layer 130; Fig. 2, para 0016] that is electrically connected to the semiconductor structure [D10/D11] and contains a semiconductor material [130 can be silicon; para 0020];
a decoupling capacitor [decoupling capacitor Cd, between package substrate 120 and circuit board 110; Fig. 2, para 0021] having a first surface [top surface of Cd] and an opposing second surface [bottom surface of Cd]; and
a circuit board [110].
However, Yang does not explicitly teach:
wherein the decoupling capacitor contains alternating dielectric layers and internal electrode layers, the internal electrode layers containing first internal electrode layers and second internal electrode layers, wherein the capacitor further contains a first external terminal that is electrically connected to the first internal electrode layers and disposed on the first surface of the capacitor, a second external terminal that is electrically connected to the first internal electrode layers and disposed on the second surface of the capacitor, a third external terminal that is electrically connected to the second internal electrode layers and disposed on the first surface of the capacitor, and a fourth external terminal that is electrically connected to the second internal electrode layers and disposed on the second surface of the capacitor, wherein the first external terminal and the third external terminal are electrically connected to the interposer;
a circuit board, wherein the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the circuit board.
Yang and Berolini teach wherein the decoupling capacitor [capacitor 408; Fig. 2, para 0018 of Berolini] contains alternating dielectric layers [dielectric layers; Fig. 2, para 0070 of Berolini] and internal electrode layers [internal electrode layers 205/215; Fig. 2, para 0070 of Berolini], the internal electrode layers [205/215 of Berolini] containing first internal electrode layers [205 of Berolini] and second internal electrode layers [215 of Berolini], wherein the capacitor further contains a first external terminal [top left external terminal of 408; Fig. 2, para 0018 of Berolini] that is electrically connected to the first internal electrode layers [205 of Berolini] and disposed on the first surface [top surface of Cd of Berolini] of the capacitor, a second external terminal [bottom left external terminal of 408; Fig. 2, para 0018 of Berolini] that is electrically connected to the first internal electrode layers [205] and disposed on the second surface [bottom surface of Cd of Berolini] of the capacitor, a third external terminal [top right external terminal of 408; Fig. 2, para 0018 of Berolini] that is electrically connected to the second internal electrode layers [215 of Berolini] and disposed on the first surface [top surface of Cd of Berolini] of the capacitor, and a fourth external terminal [bottom right external terminal of 408; Fig. 2, para 0018 of Berolini] that is electrically connected to the second internal electrode layers [215] and disposed on the second surface [bottom surface of Cd of Berolini] of the capacitor, wherein the first external terminal [portion of 402(4) attached to via 308 on left side of Berolini] and the third external terminal [top right external terminal of 408 of Berolini] are electrically connected to the interposer [130 of Yang];
a circuit board [110 of Yang; analogously, circuit board 406; Fig. 2, para 0019 of Berolini], wherein the second external terminal [bottom left external terminal of 408 of Berolini] and the fourth external terminal [bottom right external terminal of 408 of Berolini] of the decoupling capacitor [Cd of Berolini] are electrically connected to the circuit board [110 of Yang].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yang and Berolini before the effective filing date of the claimed invention, to include the decoupling capacitor as disclosed by Yamashita into the semiconductor device of Yang in order to obtain a semiconductor device with a decoupling capacitor with layers of electrodes and dielectrics.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with a decoupling capacitor with layers of electrodes and dielectrics to provide the predictable result of providing a smaller footprint, thereby reducing size of a circuit board [Berolini, para 0017].
In reference to claim 2, Yang and Berolini teach the invention of claim 1.
The microelectronic assembly of claim 1, wherein the semiconductor structure [D10/D11] is an integrated circuit device [para 0013 discloses D10 may be a system on a chip].
In reference to claim 3, Yang and Berolini teach the invention of claim 2.
Yang teaches The microelectronic assembly of claim 2, wherein the integrated circuit device includes a memory device, logic device, processor device, or a combination thereof [para 0013 discloses D10 may be a system on a chip, i.e. which combines memory, processor, logic device, etc.].
In reference to claim 4, Yang and Berolini teach the invention of claim 1.
Yang teaches The microelectronic assembly of claim 1, wherein the assembly contains multiple semiconductor structures [D10/D11 and D10/D21, for example; Fig. 2, para 0013].
In reference to claim 5, Yang and Berolini teach the invention of claim 4.
Yang teaches The microelectronic assembly of claim 4, wherein the semiconductor structures are arranged in an array [D10/D11 and D10/D21 are arranged in an array; Fig. 2].
In reference to claim 7, Yang and Berolini teach the invention of claim 1.
Yang teaches The microelectronic assembly of claim 1, wherein the semiconductor structure [D10/D11] is electrically connected to the interposer [130] via one or more coupling components [bumps BP3; Fig. 2, para 0018].
In reference to claim 8, Yang and Berolini teach the invention of claim 1.
Yang teaches The microelectronic assembly of claim 1, wherein one or more conductive pathways [para 0020 discloses 130 with multiple layers of wires] are formed through the semiconductor material of the interposer [130 can be silicon; para 0020].
In reference to claim 9, Yang and Berolini teach the invention of claim 8.
Yang teaches The microelectronic assembly of claim 8, wherein the conductive pathways of the interposer include through-silicon vias [para 0020 discloses 130 with silicon vias].
In reference to claim 12, Yang and Berolini teach the invention of claim 1.
Berolini teaches The microelectronic assembly of claim 1, wherein the second external terminal [bottom left external terminal of 408] and the fourth external terminal [bottom right external terminal of 408] of the decoupling capacitor [408] are directly connected to the circuit board [406].
In reference to claim 13, Yang and Berolini teach the invention of claim 1.
Yang and Berolini teach The microelectronic assembly of claim 1, further comprising a package substrate [120 of Yang] that is electrically connected to the interposer [130 of Yang], wherein the second external terminal [bottom left external terminal of 408 of Berolini] and the fourth external terminal [bottom right external terminal of 408 of 408 of Berolini] of the decoupling capacitor [Cd of Yang; 408 of Berolini] are directly connected to the circuit board [110 of Yang; 110 of Berolini].
In reference to claim 14, Yang and Berolini teach the invention of claim 13.
Yang teaches The microelectronic assembly of claim 13, wherein the package substrate [120] includes an insulating material through which one or more conductive pathways are formed [package substrates are known to have insulating material with conductive pathways].
In reference to claim 15, Yang and Berolini teach the invention of claim 14.
Yang teaches The microelectronic assembly of claim 14, wherein the insulating material is an organic material [package substrates are known to be made of organic materials].
In reference to claim 16, Yang and Berolini teach the invention of claim 1.
Berolini teaches The microelectronic assembly of claim 1, wherein the first and second external terminals have a positive polarity, and the third and fourth external terminals have a negative polarity [the external terminals on the top side of 408 vs. the bottom side of 408 would have opposite polarities].
In reference to claim 17, Yang and Berolini teach the invention of claim 1.
Berolini teaches The microelectronic assembly of claim 1, wherein at least one of the first, second, third, or fourth external terminals extend to an end surface of the capacitor [external terminals extend to end surface of 408 in a similar manner that components 702 extend toward end surface of capacitor 10 in the elected embodiment of Fig. 1 of the instant application].
In reference to claim 19, Yang and Berolini teach the invention of claim 1.
Berolini teaches The microelectronic assembly of claim 1, wherein the decoupling capacitor contains only the first external terminal and the third external terminal on the first surface [only first and third external terminals are on top side of 408; Fig. 2], and only the second external terminal and the fourth external terminal on the second surface [only second and fourth external terminals are on bottom side of 408; Fig. 2].
In reference to claim 23, Yang and Berolini teach the invention of claim 1.
Berolini teaches The microelectronic assembly of claim 1, wherein the first and the second internal electrode layers are arranged vertically [first and second external terminals are arranged vertically; Fig. 2].
In reference to claim 24, Yang and Berolini teach the invention of claim 23.
Berolini teaches The microelectronic assembly of claim 23, wherein the first internal electrode layers contain lead tabs extending to the first surface for contact with the first external terminal and lead tabs extending to the second surface for contact with the third external terminal, and further wherein the second internal electrode layers contain lead tabs extending to the first surface for contact with the second external terminal and lead tabs extending to the second surface for contact with the fourth external terminal [para 0072 disclose anchor tab of 408, i.e. anchor electrodes 305/295 that lead to the surface through vias 225/285 etc.; therefore, the tabs allow for contact to the external terminals of 408].
In reference to claim 26, Yang and Berolini teach the invention of claim 25.
Berolini teaches The microelectronic assembly of claim 25, wherein the first and the second internal electrode layers are connected to the first, second, third, and fourth external terminals through conductive vias [conductive vias 225/285; Figs. 1B-C, para 0070].
In reference to claim 27, Yang and Berolini teach the invention of claim 1.
Berolini teaches The microelectronic assembly of claim 1, wherein the dielectric layers of the decoupling capacitor [408] include a ceramic material [paras 0038, 0047, 0064, 0079 discloses ceramic material].
In reference to claim 28, Yang and Berolini teach the invention of claim 27.
Berolini teaches The microelectronic assembly of claim 27, wherein the ceramic material is a barium titanate ceramic material [para 0080 discloses ceramic and barium titanate].
In reference to claim 29, Yang and Berolini teach the invention of claim 1.
Berolini teaches The microelectronic assembly of claim 1, wherein the first, second, third, and fourth external terminals contain at least one plated layer [para 0086 discloses the external terminals may comprise plated material].
In reference to claim 30, Yang and Berolini teach the invention of claim 29.
Berolini teaches The microelectronic assembly of claim 29, wherein the plated layer is formed by a process that includes electroless plating, electrolytic plating, or a combination thereof [para 0087 discloses electroplated and electroless plated terminals].
In reference to claim 31, Yang and Berolini teach the invention of claim 1.
Yang teaches The microelectronic assembly of claim 1, wherein the circuit board [110] is electrically connected to the interposer [130] via coupling components [various coupling components connect 130 to 110; Fig. 2].
In reference to claim 32, Yang and Berolini teach the invention of claim 31.
Berolini teaches The microelectronic assembly of claim 31, wherein the coupling components include solder [paras 0018, 0025 disclose soldering].
In reference to claim 33, Yang and Berolini teach the invention of claim 1.
Yang and Berolini teach The microelectronic assembly of claim 1, wherein the first and the third external terminals [first and third external terminals of 408 of Berolini] of the decoupling capacitor [Cd of Yang; 408 of Berolini] are electrically connected to the interposer [130 of Yang] via coupling components [various coupling components connect the Cd to the 130 of Yang; Fig. 2].
In reference to claim 34, Yang and Berolini teach the invention of claim 1.
Berolini teaches The microelectronic assembly of claim 1, wherein the second and the fourth external terminals [second and fourth external terminals of 408] of the decoupling capacitor [408] are electrically connected to the circuit board [110] via coupling components [external terminals].
Examiner’s Note
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0).
Ong et al. (US-20210183755-A1) discloses capacitors directly connected to a packaging substrate and a circuit board [Fig. 2A].
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898
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