DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. US 2024/0071999 A1 in view of Chakravorty US 6,970,362 B1.
Regarding claims 1-28 and 30-33, Lin discloses:
A microelectronic assembly (Fig. 1) comprising:
a semiconductor structure (C1, C2, C3);
an active interposer (RDL1, E1, RDL2, I1, I2, TDV) that is electrically connected to the semiconductor structure (thru RDL1) and contains an insulating material (E1) within which an electronic component (I1, I2) is embedded;
a decoupling capacitor (para 0033; IPD) electrically connected to the interposer; and
a circuit board (200).
Lin does not disclose:
a decoupling capacitor having a first surface and an opposing second surface, wherein the decoupling capacitor contains alternating dielectric layers and internal electrode layers, the internal electrode layers containing first internal electrode layers and second internal electrode layers, wherein the capacitor further contains a first external terminal that is electrically connected to the first internal electrode layers and disposed on a the first surface of the capacitor, a second external terminal that is electrically connected to the first internal electrode layers and disposed on the second surface of the capacitor, a third external terminal that is electrically connected to the second internal electrode layers and disposed on the first surface of the capacitor, and a fourth external terminal that is electrically connected to the second internal electrode layers and disposed on the second surface of the capacitor, wherein the first external terminal and the third external terminal are electrically connected to the interposer; and
a circuit board, wherein the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the circuit board.
Chakravorty discloses a patent from a similar field of endeavor in which:
a decoupling capacitor (Fig. 2; 55) having a first surface (top) and an opposing second surface (opposite), wherein the decoupling capacitor contains alternating dielectric layers (53) and internal electrode layers (52/54), the internal electrode layers containing first internal electrode layers (52) and second internal electrode layers (54), wherein the capacitor further contains a first external terminal (42/44 connected to 48 and then 52) that is electrically connected to the first internal electrode layers and disposed on a the first surface of the capacitor, a second external terminal (56/58 connected to 48 and the 52) that is electrically connected to the first internal electrode layers and disposed on the second surface of the capacitor, a third external terminal (42/44 connected to 49 and then 54) that is electrically connected to the second internal electrode layers and disposed on the first surface of the capacitor, and a fourth external terminal (56/58 connected to 49 and then 54) that is electrically connected to the second internal electrode layers and disposed on the second surface of the capacitor, wherein the first external terminal and the third external terminal are electrically connected to an overlying die (40); and
a circuit board (60), wherein the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the circuit board (Fig. 2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the decoupling capacitor of Chakravorty as the IPD structure in Lin’s reference such that the first and third terminals of the decoupling capacitor are electrically connected the interposer and the second and fourth terminals are electrically connected to the circuit board. Such in inclusion would allow a reduction in switching noise in high-speed integrated circuits that may be accommodated in the microelectronic assembly.
(claims 2-6) Lin; para 0025.
(claim 7) Lin; one or more coupling components (B1).
(claim 8) Lin; one or more conductive pathways (TDVs).
(claim 9) Lin; para 0018.
(claims 10-12) Lin; para 0015.
(claims 13-14) Lin; a package substrate (RDL; para 0013).
(claim 15) Chakravorty; a positive polarity (Vcc) and a negative polarity (Vss).
(claims 16-18) Chakravorty; 42/44 and 56/58.
(claims 19-21) Chakravorty; Fig. 2., col 4 line 61 to col 5 line 9.
(claims 22-23) Chakravorty; first internal electrode layers contain lead tabs (48); second internal electrode layers contain lead tabs (49).
(claims 24-25) Chakravorty; Fig. 2, 48 and 49.
(claims 26-27) Chakravorty; col 4 line 4-14.
(claim 28) Chakravorty; Fig. 2, 44 and 56.
(claims 30-31) Chakravorty; Fig. 2, B2.
(claims 32) Chakravorty; Fig. 2, 42, 44 electrically connected to Lin; RDL2.
(claims 33) Chakravorty; Fig. 2, 56, 58 electrically connected to 60.
Regarding claim 29, the examiner does not give patentable weight in regards to the claim limitation stating that “wherein the plated layer is formed by a process that includes electroless plating, electrolytic plating, or a combination thereof” since such a limitation is taken to be a product-by-process limitation and is considered nonlimiting. A product by process claim is directed to the product per se, no matter how actually made. See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al, 218 USPQ 289, 292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned" from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
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/ERROL V FERNANDES/Primary Examiner, AU 2893