DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/28/2025, 09/17/2025 and 01/15/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3,7,9,15-24,28-29 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Cain (PG Pub 2018/0330881) and Lee et al. (PG Pub 2017/0047168; hereinafter Lee).
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Regarding claim 1, refer to Fig. 2a, Fig. 2b and primarily the Examiner’s mark-up of Fig. 4 provided above, Cain teaches a semiconductor package assembly comprising:
a semiconductor structure 400;
a package substrate 406 electrically connected to the semiconductor structure (see Fig. 4); and
a capacitor 408 having a first surface (top) and an opposing second surface (bottom), wherein the capacitor contains alternating dielectric layers (not indexed; see abstract below) and internal electrode layers (not indexed; see abstract below), the internal electrode layers containing first internal electrode layers and second internal electrode layers (abstract; “ The capacitor includes a main body containing a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers”), wherein the capacitor further contains a first external terminal (annotated “t1” in Fig. 4 above) that is electrically connected to the first internal electrode layers and disposed on a first surface of the capacitor (see Fig.4 and abstract), a second external terminal (annotated “t2” in Fig. 4 above) that is electrically connected to the first internal electrode layers and disposed on the second surface of the capacitor (see Fig.4 and abstract), a third external terminal (annotated “t3” in Fig. 4 above) that is electrically connected to the second internal electrode layers and disposed on the first surface of the capacitor (see Fig.4 and abstract), and a fourth external terminal (annotated “t4” in Fig. 4 above) that is electrically connected to the second internal electrode layers and disposed on the second surface of the capacitor (see Fig.4 and abstract), wherein the first external terminal and the third external terminal are electrically connected to the semiconductor structure, and the second external terminal and the fourth external terminal are electrically connected to the package substrate (see Fig. 4).
Although, Cain teaches the capacitor he does not teach the material composition of the capacitor is ceramic.
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In the same field of endeavor, refer to Fig. 6 and Fig. 4-provided above, Lee teaches a multilayer ceramic capacitor comprising:
a first surface (bottom) and an opposing second surface (top), wherein the ceramic capacitor contains alternating dielectric layers 11 and internal electrode layers 21,22, the internal electrode layers containing first internal electrode layers 21 and second internal electrode layers 22, wherein the capacitor further contains a first external terminal 31 that is electrically connected to the first internal electrode layers (para [0050]) and disposed on the first surface of the capacitor (see Fig. 4 and Fig. 6), a second external terminal 34 that is electrically connected to the first internal electrode layers and disposed on the second surface of the capacitor (see Fig. 4 and Fig. 6), a third external terminal 32 that is electrically connected to the second internal electrode layers and disposed on the first surface of the capacitor (see Fig. 4 and Fig. 6), and a fourth external terminal 35 that is electrically connected to the second internal electrode layers (see Fig. 4 and Fig. 6) and disposed on the second surface of the capacitor.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the capacitor of Cain with the multi-layered ceramic capacitor, as taught by Lee, to better control/decrease acoustic noise (para [0010-0013]).
Regarding claim 2, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the semiconductor structure 400 is an integrated circuit device (see Fig. 4 and para [0027]).
Regarding claim 3, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the integrated circuit device 400 includes a memory device, logic device, processor device (para [0027]), or a combination thereof.
Regarding claim 7, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the package substrate 406 includes an insulating material through which one or more conductive pathways are formed (para [0026]; “406 that contains a substrate (e.g., insulating layer) having an upper surface and a lower surface. The circuit board 406 has a plurality of electrical current paths (not shown)”), wherein the conductive pathways are in electrical connection with the second and fourth external terminals of the ceramic capacitor (see Fig. 4).
Regarding claim 9, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches an interposer 402 electrically connected to the semiconductor structure 400 and the package substrate 406, wherein the first external terminal (“t1”) and the third external terminal (“t3”) are electrically connected to the interposer (see Fig. 4).
Regarding claim 15, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the first (“t1”) and second external terminals (“t2”) have a positive polarity, and the third (“t3”) and fourth (“t4”) external terminals have a negative polarity (see Fig. 2a and Fig. 2b).
Regarding claim 16, refer to the figures cited above, the combination of Cain and Lee teach at least one of the first (“t1”), second (“t2”), third (“t3”), or fourth (“t4”) external terminals extend to an end surface of the capacitor (see Fig. 4).
Regarding claim 17, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the first, second, third, and fourth external terminals (“t1”), second (“t2”), third (“t3”), or fourth (“t4”) do not extend to an end surface of the capacitor (see Fig. 2a).
Regarding claim 18, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the ceramic capacitor contains only the first external terminal and the third external terminal on the first surface, and only the second external terminal and the fourth external terminal on the second surface (see Fig. 4 and para [0058]).
Regarding claim 19, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the capacitor contains at least four external terminals (22,24) on the first surface (see Fig. 4-Cain) and at least four external terminals (22,24) on the second surface (see Fig. 4-Cain).
Regarding claim 20, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the external terminals (22,24) are arranged in a linear fashion on the first surface (top) and the second surface (bottom) (see Fig. 4-Cain).
Regarding claim 21, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the external terminals (22,24) are arranged in a multi-dimensional array (2 x 4 array) on the first surface (top) and the second surface (bottom) (see Fig. 4).
Regarding claim 22, refer to the figures cited above, in the combination of Cain and Lee, Lee teaches the first 21b and the second internal electrode 22b layers are arranged vertically (see Fig. 6).
Regarding claim 23, refer to the figures cited above, in the combination of Cain and Lee, Lee teaches the first internal electrode layers 21b contain lead tabs (vertical portions of 21b extending up) extending to the first surface (top) for contact with the first external terminal (e.g. 34) and lead tabs (vertical portions of 21b extending down) extending to the second surface (bottom) for contact with the third external terminal (see cited figures), and further wherein the second internal electrode layers contain lead tabs extending to the first surface for contact with the second external terminal and lead tabs extending to the second surface for contact with the fourth external terminal (same analysis for 22b).
Regarding claim 24, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the first 130 and the second internal electrode 140 layers are arranged horizontally (see Fig. 1c).
Regarding claim 28, refer to the figures cited above, in the combination of Cain and Lee, Lee teaches the first 34, second 31, third 35, and fourth 32 external terminals contain at least one plated layer (see Fig. 4).
Note: the limitation “at least one plated layer" as cited is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. While not objectionable, the Office reminds Applicant that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how they are actually made. In re Hirao, 190 USPQ 15 at 17. See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that applicant has the burden of proof in such cases, as the above case law makes clear. See also MPEP 706.03(e) and MPEP 2113 [R-1]; thus, no patentable weight will be given to those process steps which do not add structural limitations to the final product.
Regarding claim 29, refer to the figures cited above, in the combination of Cain and Lee, Lee teaches the plated layer (terminals) is formed (see Fig. 4) by a process that includes electroless plating, electrolytic plating, or a combination thereof.
Note: the limitation “the plated layer is formed by a process that includes electroless plating, electrolytic plating, or a combination thereof" as cited is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. While not objectionable, the Office reminds Applicant that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how they are actually made. In re Hirao, 190 USPQ 15 at 17. See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that applicant has the burden of proof in such cases, as the above case law makes clear. See also MPEP 706.03(e) and MPEP 2113 [R-1]; thus, no patentable weight will be given to those process steps which do not add structural limitations to the final product.
Regarding claim 32, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the second and the fourth external terminals (“t1-t4”) of the ceramic capacitor 408 are electrically connected to the package substrate via coupling components (solder) (see Fig. 4).
2. Claim(s) 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Cain and Lee, as applied to claim 1 above, and further in view of Pi (PG Pub 2022/0254699).
Regarding claim 4, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the assembly contains a semiconductor structure 400, he does not teach it comprises “multiple semiconductor structures.”
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In the same field of endeavor, refer to Fig. 1a-provided above, Pi teaches a semiconductor device 100 comprising: multiple semiconductor structures 109a,109b,111 (para [0036]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate additional semiconductor structures, as taught by Pi, to create a more robust package.
Regarding claim 5, refer to the figures cited above, in the combination of Cain, Lee and Pi, Pi teaches the semiconductor structures 109a,109b,111 are arranged in an array (see Fig. 1a).
3. Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cain, Lee and Pi, as applied to claim 4 above, and further in view of Zhang et al. (PG Pub 2020/0365554; hereinafter Zhang).
Regarding claim 6, refer to the figures cited above, in the combination of Cain, Lee and Pi, Although, Pi teaches the horizontal array of semiconductor structures he does not explicitly teach “the semiconductor structures are stacked.”
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In the same field of endeavor, refer to Fig. 10-provided above, Zhang teaches a semiconductor device 100 comprising: multiple semiconductor structures 132; wherein the semiconductor structures are stacked (see Fig. 10).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate additional semiconductor structures, as taught by Pi, to create a more robust package.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cain and Lee, as applied to claim 7 above, and further in view of Silvano De Sousa et al. (PG Pub 2019/0223298; hereinafter Silvano De Sousa).
Regarding claim 8, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the insulating material (para [0026]). He does not explicitly teach he material composition of the insulating material “includes an organic material, inorganic material, semiconductor material, or a combination thereof.”
In the same field of endeavor, Silvano De Sousa teaches a package substrate comprising inorganic materials (para [0063]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the package substrate of Cain comprise inorganic materials, as taught by Silvano De Sousa, to provide the benefit of being flame retardant (para [0007]).
4. Claim(s) 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Cain and Lee, as applied to claim 9 above, and further in view of Mallik et al. (PG Pub 2020/0395313; hereinafter Mallik).
Regarding claim 10, claim 11, claim 12, claim 13 and claim 14, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the interposer 402 includes conductive pathways are in electrical connection with the first (“t1”) and third (“t3”) external terminals of the ceramic capacitor 408, he does not explicitly teach the details of the interposer as (Regarding claim 10) the interposer includes an insulating material through which one or more conductive pathways are formed; (Regarding claim 11) wherein the insulating material includes an organic material, inorganic material, semiconductor material, or a combination thereof; (Regarding claim 12) wherein an electronic component is embedded within the interposer; and (Regarding claim 13) wherein the electronic component includes a capacitor, resistor, inductor, fuse, diode, transformer, sensor, electrostatic discharge device, memory device, radio frequency device, power amplifier, power management device, antenna, microelectromechanical system, or a combination thereof; and (Regarding claim 14) wherein the capacitor is embedded within the interposer.
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In the same field of endeavor, refer to Fig. 1a provided above, Mallik teaches an interposer 130 comprising:
(Regarding claim 10) an insulating material (para [0094]) through which one or more conductive pathways 134 are formed (see Fig. 1a);
(Regarding claim 11) wherein the insulating material includes an organic material, inorganic material, semiconductor material, or a combination thereof (para [0094]);
(Regarding claim 12) wherein an electronic component 140 is embedded within the interposer (see Fig. 1a);
(Regarding claim 13) wherein the electronic component includes a capacitor, resistor, inductor, fuse, diode, transformer, sensor, electrostatic discharge device, memory device, radio frequency device, power amplifier, power management device, antenna, microelectromechanical system, or a combination thereof (para 0036]); and
(Regarding claim 14) wherein the capacitor is embedded within the interposer (see Fig. 1a).
(para [0036]; “an active nested component 140 may comprise logic devices, analog/RF devices, I/O circuits, memory devices, voltage regulators, sensors, or the like. Passive nested components 140 may comprise high density multi-die interconnect bridge dies, capacitors, inductors, resistors, thermo-electric coolers, high speed connectors, or the like.”).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the interposer package of Cain with the heterogeneous nested interposer package containing the capacitor, as taught by Mallik, to allow for high yields and reliability, even when fine pitched interconnects are used (e.g., when the nested component is a bridge between two dies) (para [0033]).
5. Claim(s) 30-31 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Cain and Lee, as applied to claim 9 above, and further in view of Chhabra et al. (PG Pub 2019/0370425; hereinafter Chhabra).
Regarding claim 30 and claim 31, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the package substrate. He does not explicitly teach (Regarding claim 30) a circuit board 108 that is electrically connected to a package substrate 118 via coupling components119; (Regarding claim 31) wherein the coupling components 1196 include solder
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In the same field of endeavor, refer to Fig. 1 provided above, Chhabra teaches a semiconductor device 100 comprising:
(Regarding claim 30) a circuit board 108 that is electrically connected to a package substrate 118 via coupling components119;
(Regarding claim 31) wherein the coupling components 1196 include solder (see Fig. 1).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the package substrate of Cain, to a PCB as taught by Chhabra, to provide power to the package.
Regarding claim 33, refer to the figures cited above, in the combination of Cain and Lee, Cain teaches the package substrate. He does not explicitly teach a circuit board, wherein the package substrate is electrically connected to the circuit board.
In the same field of endeavor, refer to Fig. 1 provided above, Chhabra teaches a semiconductor device 100 comprising: a circuit board 108 that is electrically connected to a package substrate 118 via coupling components 119.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the package substrate of Cain, to a PCB as taught by Chhabra, to provide power to the package.
Allowable Subject Matter
6. Claims 25-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 25 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 25, the first and the second internal electrode layers are connected to the first, second, third, and fourth external terminals through conductive vias.
Claim 26 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 26, the dielectric layers of the ceramic capacitor include a ceramic material. Claim 27 would be allowable, because it depends on allowable claim 26.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817