Prosecution Insights
Last updated: August 17, 2026
Application No. 18/494,849

CIRCUIT BOARD ASSEMBLY AND ELECTRONIC DEVICE

Final Rejection §103
Filed
Oct 26, 2023
Priority
Apr 27, 2021 — CN 202110457497.X +1 more
Examiner
TSO, STANLEY
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Huawei Technologies Co., Ltd.
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
384 granted / 506 resolved
+7.9% vs TC avg
Strong +33% interview lift
Without
With
+33.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
40 currently pending
Career history
534
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
53.3%
+13.3% vs TC avg
§102
25.8%
-14.2% vs TC avg
§112
16.3%
-23.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 506 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over “Chengalva” (US 2005/0109534) in view of “Thanu” (US 2018/0350712). Regarding claim 1, Chengalva discloses 1. A circuit board assembly, comprising: a circuit board (Fig. 1, [0013], [0017]; the printed circuit board 12); a substrate fastened to a side of the circuit board (Fig. 1, [0013], [0017]; the stiffener 24 is fastened to a side of the printed circuit board 12), wherein the circuit board has a first coefficient of thermal expansion (Fig. 1, [0013], [0017]; the printed circuit board 12 has a CTE of 17 ppm/EC), the substrate has a second coefficient of thermal expansion (Fig. 1, [0013], [0017]; the stiffener 24 has a CTE of 16 ppm/EC), and a difference between the second coefficient of thermal expansion of the substrate, and the first coefficient of thermal expansion of the circuit board, is less than or equal to 30% of the first coefficient of thermal expansion of the circuit board (Fig. 1, [0013], [0017]; the difference between the CTE of the stiffener 24 and the CTE of the printed circuit board 12 is 1 ppm/EC, which is less than or equal to 30% of the CTE of the printed circuit board 12). Chengalva does not disclose a holder and therefore does not disclose any limitations of claim 1 that relate to the holder. Thanu discloses a holder, wherein the holder is located on a side of the circuit board facing away from the substrate, two ends of the holder are fastened to the two ends of the circuit board (Fig. 1, [0019]; the heat dissipation device 140 is a holder located on a component side of the circuit board 110, two ends of the heat dissipation device 140 are fastened to the two ends of the circuit board 110), an open gap is formed directly between a middle part of the holder and a middle part of the circuit board to accommodate deformation of the circuit board, wherein the middle part of the holder is spaced apart from and unfastened to the middle part of the circuit board (Fig. 1, [0019]; an open gap is formed directly between a middle part of the heat dissipation device 140 and a middle part of the circuit board 110 to accommodate deformation of the circuit board 110, wherein the middle part of the heat dissipation device 140 is spaced apart from and unfastened to the middle part of the circuit board 110. Examiner’s note: the limitation: “to accommodate deformation of the circuit board” is construed as having the ability to perform. Thanu’s open gap is able to accommodate deformation of the circuit board, therefore Thanu teaches this limitation.), and a coefficient of thermal expansion of the holder is less than a coefficient of thermal expansion of the circuit board (Fig. 1, [0019]; the heat dissipation device 140 is made from copper which has a CTE of 16.5 ppm/EC, which is less than a circuit board which has a CTE of 17 ppm/EC). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Chengalva’s circuit board assembly with Thanu’s holder in order to develop heat dissipation device configurations to address the various issues with regard to multiple microelectronic devices, as suggested by Thanu at [0007]. Regarding claim 17, Chengalva discloses 17. A circuit board assembly, comprising: a circuit board (Fig. 1, [0013], [0017]; the printed circuit board 12); a substrate; wherein the substrate is fastened to the circuit board (Fig. 1, [0013], [0017]; the stiffener 24 is fastened to a side of the printed circuit board 12). Chengalva does not disclose a holder and therefore does not disclose any limitations of claim 17 that relate to the holder. Thanu discloses a holder, the holder is located on a side of the circuit board facing away from the substrate, two ends of the holder are fastened to two ends of the circuit board (Fig. 1, [0019]; the heat dissipation device 140 is a holder located on a component side of the circuit board 110, two ends of the heat dissipation device 140 are fastened to the two ends of the circuit board 110), an open gap is formed directly between a middle part of the holder and a middle part of the circuit board to accommodate deformation of the circuit board, wherein the middle part of the holder is spaced apart from and unfastened to the middle part of the circuit board (Fig. 1, [0019]; an open gap is formed directly between a middle part of the heat dissipation device 140 and a middle part of the circuit board 110 to accommodate deformation of the circuit board 110, wherein the middle part of the heat dissipation device 140 is spaced apart from and unfastened to the middle part of the circuit board 110. Examiner’s note: the limitation: “to accommodate deformation of the circuit board” is construed as having the ability to perform. Thanu’s open gap is able to accommodate deformation of the circuit board, therefore Thanu teaches this limitation.), and a coefficient of thermal expansion of the holder is less than a coefficient of thermal expansion of the circuit board (Fig. 1, [0019]; the heat dissipation device 140 is made from copper which has a CTE of 16.5 ppm/EC, which is less than a circuit board which has a CTE of 17 ppm/EC). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Chengalva’s circuit board assembly with Thanu’s holder in order to develop heat dissipation device configurations to address the various issues with regard to multiple microelectronic devices, as suggested by Thanu at [0007]. Regarding claim 19, Chengalva discloses 19. An electronic device, comprising: a circuit board assembly, the circuit board assembly comprising: a circuit board (Fig. 1, [0013], [0017]; the printed circuit board 12); a substrate fastened to a side of the circuit board (Fig. 1, [0013], [0017]; the stiffener 24 is fastened to a side of the printed circuit board 12), wherein the circuit board has a first coefficient of thermal expansion (Fig. 1, [0013], [0017]; the printed circuit board 12 has a CTE of 17 ppm/EC), the substrate has a second coefficient of thermal expansion (Fig. 1, [0013], [0017]; the stiffener 24 has a CTE of 16 ppm/EC), and a difference between the second coefficient of thermal expansion of the substrate, and the first coefficient of thermal expansion of the circuit board, is less than or equal to 30% of the first coefficient of thermal expansion of the circuit board (Fig. 1, [0013], [0017]; the difference between the CTE of the stiffener 24 and the CTE of the printed circuit board 12 is 1 ppm/EC, which is less than or equal to 30% of the CTE of the printed circuit board 12), wherein the circuit board assembly further comprises a chip fastened to a side of the circuit board facing away from the substrate (Fig. 1, [0013], [0017]; the surface mount component 18 is fastened to a side of the printed circuit board 12 facing away from the stiffener 24). Chengalva does not disclose a holder and therefore does not disclose any limitations of claim 19 that relate to the holder. Thanu discloses a holder, wherein the holder is located on a side of the circuit board facing away from the substrate, two ends of the holder are fastened to the two ends of the circuit board (Fig. 1, [0019]; the heat dissipation device 140 is a holder located on a component side of the circuit board 110, two ends of the heat dissipation device 140 are fastened to the two ends of the circuit board 110), an open gap is formed directly between a middle part of the holder and a middle part of the circuit board to accommodate deformation of the circuit board, wherein the middle part of the holder is spaced apart from and unfastened to the middle part of the circuit board (Fig. 1, [0019]; an open gap is formed directly between a middle part of the heat dissipation device 140 and a middle part of the circuit board 110 to accommodate deformation of the circuit board 110, wherein the middle part of the heat dissipation device 140 is spaced apart from and unfastened to the middle part of the circuit board 110. Examiner’s note: the limitation: “to accommodate deformation of the circuit board” is construed as having the ability to perform. Thanu’s open gap is able to accommodate deformation of the circuit board, therefore Thanu teaches this limitation.), and a coefficient of thermal expansion of the holder is less than a coefficient of thermal expansion of the circuit board (Fig. 1, [0019]; the heat dissipation device 140 is made from copper which has a CTE of 16.5 ppm/EC, which is less than a circuit board which has a CTE of 17 ppm/EC). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Chengalva’s circuit board assembly with Thanu’s holder in order to develop heat dissipation device configurations to address the various issues with regard to multiple microelectronic devices, as suggested by Thanu at [0007]. Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chengalva in view of Thanu and “Ong” (US 2022/0068841). Regarding claim 6, Chengalva in view of Thanu discloses the claimed invention as applied to claim 1, above. Chengalva does not disclose the limitations of claim 6. Ong discloses the holder comprises an upper holder and a lower holder (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is an upper holder and it includes a dielectric layer 220 which is a lower holder), wherein the upper holder and the lower holder are stacked and fastened (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 and the dielectric layer 220 are stacked and fastened), the upper holder is located on a side of the lower holder facing away from the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is located on a side of the dielectric layer 220 facing away from the printed circuit board 206), two ends of at least one of the upper holder and the lower holder are fastened to the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; two ends of the stiffener member 214 and the dielectric layer 220 are fastened to the printed circuit board 206), a gap is formed between a middle part of the lower holder and a middle part of the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; a gap is formed between a middle part of the dielectric layer 220 and a middle part of the printed circuit board 206), and a coefficient of thermal expansion of the upper holder is less than a coefficient of thermal expansion of the lower holder (Fig. 2A, [0030], [0035], [0038]-[0039]; the CTE of the stiffener member 214, a stainless-steel frame which has a CTE of 16 ppm/EC is less than the CTE of the dielectric layer 220 which is epoxy or other dielectrics which have a CTE of 30-200 ppm/EC). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Chengalva’s circuit board assembly, as modified by Thanu, with Ong’s holder in order to achieve platform miniaturization through package substrate and/or PCB real-estate reduction, as suggested by Ong at [0016]. Regarding claim 18, Chengalva in view of Thanu discloses the claimed invention as applied to claim 17, above. Chengalva does not disclose the limitations of claim 18. Ong discloses the holder comprises an upper holder and a lower holder (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is an upper holder and it includes a dielectric layer 220 which is a lower holder), wherein the upper holder and the lower holder are stacked and fastened (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 and the dielectric layer 220 are stacked and fastened), the upper holder is located on a side of the lower holder facing away from the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is located on a side of the dielectric layer 220 facing away from the printed circuit board 206), two ends of at least one of the upper holder and the lower holder are fastened to the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; two ends of the stiffener member 214 and the dielectric layer 220 are fastened to the printed circuit board 206), a gap is formed between a middle part of the lower holder and a middle part of the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; a gap is formed between a middle part of the dielectric layer 220 and a middle part of the printed circuit board 206), and a coefficient of thermal expansion of the upper holder is less than a coefficient of thermal expansion of the lower holder (Fig. 2A, [0030], [0035], [0038]-[0039]; the CTE of the stiffener member 214, a stainless-steel frame which has a CTE of 16 ppm/EC is less than the CTE of the dielectric layer 220 which is epoxy or other dielectrics which have a CTE of 30-200 ppm/EC). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Chengalva’s circuit board assembly, as modified by Thanu, with Ong’s holder in order to achieve platform miniaturization through package substrate and/or PCB real-estate reduction, as suggested by Ong at [0016]. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chengalva in view of Thanu and “”Colbert” (US 2008/0009152). Regarding claim 20, Chengalva in view of Thanu discloses the claimed invention as applied to claim 1, above. Chengalva does not disclose the limitations of claim 20. Colbert discloses the two ends of the holder are fastened to the two ends of the circuit board by a plurality of fasteners, wherein the plurality of fasteners are inserted into the circuit board and are fastened to the substrate (Fig. 2, [0024]; the two ends of the heatsink 24 are fastened to the two ends of the printed wiring board 10 by a plurality of load posts 27, wherein the plurality of load posts 27are inserted into the printed wiring board 10 and are fastened to the stiffener plate 25). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Chengalva’s circuit board assembly, as modified by Thanu, with Colbert’s fasteners in order to allow a mechanical load of the desired level to be applied to the electrical component, as suggested by Colbert at [0024]. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANLEY TSO/ Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Oct 26, 2023
Application Filed
Apr 10, 2026
Non-Final Rejection mailed — §103
Jul 08, 2026
Response Filed
Jul 27, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+33.2%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 506 resolved cases by this examiner. Grant probability derived from career allowance rate.

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