Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse in the reply filed on 1/9/2026 is acknowledged. The traversal is on the grounds that Species VII is allegedly inclusive of the features presented in Figs. 1, 2A and 9-11. This is not found persuasive because Species VII (figure 10) is an embodiment where the fastener 34d is in direct connection with both the holder 38d and the circuit board 32d; whereas Species VI (figure 9) is an embodiment where the fastener 34d is in direct connection with the holder 38d; and whereas Species I (figure 2A) is an embodiment where the fastener 34d is in direct connection with the circuit board 32d. Therefore, the Examiner respectfully submits that Species I, VI and VII are distinct. As such, the Examiner respectfully disagrees with Applicant’s allegations that the requirement to elect a distinct species is not proper.
The requirement is still deemed proper and is therefore made FINAL.
EXAMINER'S AMENDMENT
In the response dated 1/9/2026, Applicant elected Species VII, which allegedly includes claims 1, 5-6, 10-11 and 15-19. This is interpreted to mean that Applicant considers that Species VII does not include claims 2-4, 7-9 and 12-14. Accordingly, claims 2-4, 7-9 and 12-14 are deemed withdrawn.
It is noted that claims 10-11 depend from independent claim 7, which is deemed withdrawn. Therefore, claims 10-11 are also deemed withdrawn.
Similarly, claims 15-16 depend from independent claim 12, which is deemed withdrawn. Therefore, claims 15-16 are also deemed withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 19 rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Chengalva” (US 2005/0109534).
Regarding claim 1, Chengalva anticipates 1. A circuit board assembly, comprising: a circuit board (Fig. 1, [0013], [0017]; the printed circuit board 12);
and a substrate fastened to a side of the circuit board (Fig. 1, [0013], [0017]; the stiffener 24 is fastened to a side of the printed circuit board 12),
wherein the circuit board has a first coefficient of thermal expansion (Fig. 1, [0013], [0017]; the printed circuit board 12 has a CTE of 17 ppm/EC),
the substrate has a second coefficient of thermal expansion (Fig. 1, [0013], [0017]; the stiffener 24 has a CTE of 16 ppm/EC),
and a difference between the second coefficient of thermal expansion of the substrate, and the first coefficient of thermal expansion of the circuit board, is less than or equal to 30% of the first coefficient of thermal expansion of the circuit board (Fig. 1, [0013], [0017]; the difference between the CTE of the stiffener 24 and the CTE of the printed circuit board 12 is 1 ppm/EC, which is less than or equal to 30% of the CTE of the printed circuit board 12).
Regarding claim 19, Chengalva anticipates 19. An electronic device, comprising: a circuit board assembly, the circuit board assembly comprising: a circuit board (Fig. 1, [0013], [0017]; the printed circuit board 12);
and a substrate fastened to a side of the circuit board (Fig. 1, [0013], [0017]; the stiffener 24 is fastened to a side of the printed circuit board 12),
wherein the circuit board has a first coefficient of thermal expansion (Fig. 1, [0013], [0017]; the printed circuit board 12 has a CTE of 17 ppm/EC),
the substrate has a second coefficient of thermal expansion (Fig. 1, [0013], [0017]; the stiffener 24 has a CTE of 16 ppm/EC),
and a difference between the second coefficient of thermal expansion of the substrate, and the first coefficient of thermal expansion of the circuit board, is less than or equal to 30% of the first coefficient of thermal expansion of the circuit board (Fig. 1, [0013], [0017]; the difference between the CTE of the stiffener 24 and the CTE of the printed circuit board 12 is 1 ppm/EC, which is less than or equal to 30% of the CTE of the printed circuit board 12),
wherein the circuit board assembly further comprises a chip fastened to a side of the circuit board facing away from the substrate (Fig. 1, [0013], [0017]; the surface mount component 18 is fastened to a side of the printed circuit board 12 facing away from the stiffener 24).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5-6 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chengalva in view of “Ong” (US 2022/0068841).
Regarding claim 5, Chengalva discloses the claimed invention as applied to claim 1, above.
Chengalva does not disclose the limitations of claim 5.
Ong discloses 5. The circuit board assembly according to claim 1, further comprising: a holder (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is a stainless-steel frame which has a CTE of 16 ppm/EC),
wherein the holder is located on a side of the circuit board facing away from the substrate (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is located on a side of the printed circuit board 206 as the package substrate 202, which is the side of Chengalva’s circuit board facing away from the substrate),
two ends of the holder are fastened to the two ends of the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; two ends of the stiffener member 214 are fastened to two ends of the printed circuit board 206),
a gap is formed between a middle part of the holder and a middle part of the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; a gap is formed between a middle part of the stiffener member 214 and a middle part of the printed circuit board 206),
and a coefficient of thermal expansion of the holder is less than a coefficient of thermal expansion of the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is a stainless-steel frame which has a CTE of 16 ppm/EC which is less than the CTE of Chengalva’s circuit board).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Chengalva’s circuit board assembly with Ong’s holder in order to achieve platform miniaturization through package substrate and/or PCB real-estate reduction, as suggested by Ong at [0016].
Regarding claim 6, Chengalva in view of Ong discloses the claimed invention as applied to claim 5, above.
Chengalva does not disclose the limitations of claim 6.
Ong discloses 6. The circuit board assembly according to claim 5, wherein the holder comprises an upper holder and a lower holder (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is an upper holder and it includes a dielectric layer 220 which is a lower holder),
wherein the upper holder and the lower holder are stacked and fastened (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 and the dielectric layer 220 are stacked and fastened),
the upper holder is located on a side of the lower holder facing away from the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is located on a side of the dielectric layer 220 facing away from the printed circuit board 206),
two ends of at least one of the upper holder and the lower holder are fastened to the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; two ends of the stiffener member 214 and the dielectric layer 220 are fastened to the printed circuit board 206),
a gap is formed between a middle part of the lower holder and a middle part of the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; a gap is formed between a middle part of the dielectric layer 220 and a middle part of the printed circuit board 206),
and a coefficient of thermal expansion of the upper holder is less than a coefficient of thermal expansion of the lower holder (Fig. 2A, [0030], [0035], [0038]-[0039]; the CTE of the stiffener member 214, a stainless-steel frame which has a CTE of 16 ppm/EC is less than the CTE of the dielectric layer 220 which is epoxy or other dielectrics which have a CTE of 30-200 ppm/EC).
Regarding claim 17, Chengalva discloses 17. A circuit board assembly, comprising: a circuit board (Fig. 1, [0013], [0017]; the printed circuit board 12);
a substrate; wherein the substrate is fastened to the circuit board (Fig. 1, [0013], [0017]; the stiffener 24 is fastened to a side of the printed circuit board 12).
Chengalva does not disclose a holder and therefore does not disclose any limitations of claim 17 that relate to the holder.
Ong discloses a holder, the holder is located on a side of the circuit board facing away from the substrate (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is located on a side of the printed circuit board 206 as the package substrate 202, which is the side of Chengalva’s circuit board facing away from the substrate),
two ends of the holder are fastened to two ends of the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; two ends of the stiffener member 214 are fastened to two ends of the printed circuit board 206),
a gap is formed between a middle part of the holder and a middle part of the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; a gap is formed between a middle part of the stiffener member 214 and a middle part of the printed circuit board 206),
and a coefficient of thermal expansion of the holder is less than a coefficient of thermal expansion of the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is a stainless-steel frame which has a CTE of 16 ppm/EC which is less than the CTE of Chengalva’s circuit board).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Chengalva’s circuit board assembly with Ong’s holder in order to achieve platform miniaturization through package substrate and/or PCB real-estate reduction, as suggested by Ong at [0016].
Regarding claim 18, Chengalva in view of Ong discloses the claimed invention as applied to claim 17, above.
Chengalva does not disclose the limitations of claim 17.
Ong discloses 18. The circuit board assembly according to claim 17, wherein the holder comprises an upper holder and a lower holder (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is an upper holder and it includes a dielectric layer 220 which is a lower holder),
wherein the upper holder and the lower holder are stacked and fastened (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 and the dielectric layer 220 are stacked and fastened),
the upper holder is located on a side of the lower holder facing away from the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; the stiffener member 214 is located on a side of the dielectric layer 220 facing away from the printed circuit board 206),
two ends of at least one of the upper holder and the lower holder are fastened to the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; two ends of the stiffener member 214 and the dielectric layer 220 are fastened to the printed circuit board 206),
a gap is formed between a middle part of the lower holder and a middle part of the circuit board (Fig. 2A, [0030], [0035], [0038]-[0039]; a gap is formed between a middle part of the dielectric layer 220 and a middle part of the printed circuit board 206),
and a coefficient of thermal expansion of the upper holder is less than a coefficient of thermal expansion of the lower holder (Fig. 2A, [0030], [0035], [0038]-[0039]; the CTE of the stiffener member 214, a stainless-steel frame which has a CTE of 16 ppm/EC is less than the CTE of the dielectric layer 220 which is epoxy or other dielectrics which have a CTE of 30-200 ppm/EC).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STANLEY TSO/Primary Examiner, Art Unit 2847
Prosecution Insights