DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 03/20/2026. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 01/22/2024.
Oath/Declaration
The oath or declaration filed on 12/04/2023 is acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/26/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Election/Restrictions
Applicant’s election, with traverse, group I, Species I (Fig 1): claims 1-10, in the “Response to Election / Restriction Filed” filed on 03/20/2026 is acknowledged. The traversal is on the ground(s) that device/method claims are mirror identical and Species I to species III are not directed to patentably distinct species and fails to demonstrate a serious search burden. Thus, Applicant requests that the restriction requirement be withdrawn.
Examiner like to note that, device and methods claims are not identical as indicated office action (12/31/2025) such as “at least one valley of the corrugated part of the clip so that the mold compound forms an outer surface of the semiconductor device with the at least two peaks of the corrugated part of the clip, at least part of the flat part of the clip, and the first lead frame surface of the lead frame are exposed”.
The species require a different field of search (e.g., searching different classes/subclasses or electronic resources or non-patent language, or deploying different search queries); and/or the prior art applicable to one species would not likely be applicable to another species; and/or the species are likely to raise different non-prior art issues under U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Furthermore, the species and device/method require separate classification searches (i.e. H10W70/461 or H10W70/041 or H10W70/048 or H10W70/466 or H10W74/016 or H10W74/111 or H10W90/811 or H10W70/481 or H10W70/415 or H10W70/438) such as there are mutually exclusive features, as indicated in office action 07/22/2024 and these mutually exclusive features are categorized in the separate classes. Additionally, the species require different text searches.
The requirement is still deemed proper and is therefore made FINAL.
This office action considers claims 1-20 are thus pending for prosecution, of which, claims 11-20 are withdrawn, and claims 1-10 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Otremba et al (US 2013/0009295 A1; hereafter Otremba).
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Regarding claim 1. Otremba discloses a semiconductor device comprising:
a lead frame (Fig 3G, die pad 11, construed as lead frame, Para [ 0020]) comprising a first lead frame surface and a second lead frame surface opposite the first lead frame surface (Fig 3G, upper surface/ lower surface of die pad 11, Para [ 0020]);
a semiconductor die (Fig 3G, semiconductor chip 15, Para [ 0020]) comprising a first semiconductor die surface and a second semiconductor die surface opposite the first semiconductor die surface (Fig 3G, upper surface/ lower surface, semiconductor chip 15, Para [ 0020]);
a clip (contact clip 25, Para [ 0020]) comprising a flat part (upper surface contact clip 25, Para [ 0020]) and a corrugated part (lower surface contact clip 25, Para [ 0020]), wherein the corrugated part comprises at least two peaks and at least one valley (lower surface contact clip 25, Para [ 0020]);
a mold compound (mold material 52, Para [ 0042]);
wherein the second lead frame surface of the lead frame (Fig 3G, die pad 11, construed as lead frame, Para [ 0020]) is connected to the first semiconductor die surface of the semiconductor die (Fig 3G, semiconductor chip 15, Para [ 0020]), and wherein the second semiconductor die surface of the semiconductor die (Fig 3G, semiconductor chip 15, Para [ 0020]) is connected to the corrugated part of the clip (lower surface contact clip 25, Para [ 0020]), and wherein the mold compound (mold material 52, Para [ 0042]) encapsulates the semiconductor die (Fig 3G, semiconductor chip 15, Para [ 0020]), and the at least one valley of the corrugated part (lower surface contact clip 25, Para [ 0020]) of the clip so that the mold compound forms an outer surface of the semiconductor device (Fig 3G, semiconductor chip 15, Para [ 0020]) with the at least two peaks of the corrugated part of the clip (contact clip 25, Para [ 0020]), at least part of the flat part of the clip (upper surface contact clip 25, Para [ 0020]), and the first lead frame surface of the lead frame are exposed (Fig 3G, die pad 11, construed as lead frame, Para [ 0020]).
ALTERNATE REJECTION:
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Levardo et al (US 2020/0365549 A1; hereafter Levardo).
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Regarding claim 1. Levardo discloses a semiconductor device (Fig 2A) comprising:
a lead frame (Fig 2A, lead frame carrier 104, Para [ 0109]) comprising a first lead frame surface and a second lead frame surface opposite the first lead frame surface (Fig 2A, upper surface/ lower surface of lead frame carrier 104, Para [ 0109]);
a semiconductor die (Fig 2A, electronic component 102, Para [ 0079]) comprising a first semiconductor die surface and a second semiconductor die surface opposite the first semiconductor die surface (Fig 2A, electronic component 102, Para [ 0079]);
a clip (clip 100, Para [ 0069]) comprising a flat part (Fig 2A, carrier connection portion 112, Para [ 0069]) and a corrugated part (Fig 2A, clip 100 comprises a clip body 108, Para [ 0069]), wherein the corrugated part comprises at least two peaks and at least one valley (Fig 2A, clip 100 comprises a clip body 108, Para [ 0069]);
a mold compound (Fig 2A, mold type encapsulant 128, Para [ 0098]);
wherein the second lead frame surface of the lead frame (Fig 2A, lead frame carrier 104, Para [ 0109]) is connected to the first semiconductor die surface of the semiconductor die (Fig 2A, electronic component 102, Para [ 0079]), and wherein the second semiconductor die surface of the semiconductor die (Fig 2A, electronic component 102, Para [ 0079]) is connected to the corrugated part of the clip (Fig 2A, clip 100 comprises a clip body 108, Para [ 0069]), and wherein the mold compound (Fig 2A, mold type encapsulant 128, Para [ 0098]) encapsulates the semiconductor die (Fig 2A , electronic component 102, Para [ 0079]), and the at least one valley of the corrugated part (Fig 2A, clip 100 comprises a clip body 108, Para [ 0069]) of the clip so that the mold compound forms an outer surface of the semiconductor device (electronic component 102, Para [ 0079]) with the at least two peaks of the corrugated part of the clip (Fig 2A, clip 100 comprises a clip body 108, Para [ 0069]), at least part of the flat part of the clip (Fig 2A, carrier connection portion 112, Para [ 0069]), and the first lead frame surface of the lead frame are exposed (Fig 2A, lead frame carrier 104, Para [ 0109]).
Regarding claim 2. Levardo discloses the semiconductor device according to claim 1, Levardo further discloses wherein the second lead frame surface of the lead frame (Fig 2A, lead frame carrier 104, Para [ 0109]) is connected to the first semiconductor die surface of the semiconductor die (electronic component 102, Para [ 0079]), and/or the second semiconductor die surface of the semiconductor die is connected to the corrugated part of the clip by a method selected from the group consisting of soldering, sintering, and ultrasonic bonding.
Regarding claim 3. Levardo discloses the semiconductor device according to claim 1, Levardo further discloses wherein the mold compound (mold type encapsulant 128, Para [ 0098]) and the at least one peak of the corrugated part of the clip (clip 100 comprises a clip body 108, Para [ 0069]) forms a single planar surface.
Regarding claim 4. Levardo discloses the semiconductor device according to claim 1, Levardo further discloses wherein the lead frame and/or the clip are made of a conductive metal sheet (Para [ 0037, 0082]).
Regarding claim 6. Levardo discloses the semiconductor device according to claim 1, Levardo further discloses wherein the corrugated part of the clip comprises three or four peaks (clip 100 comprises a clip body 108, Para [ 0069]).
Regarding claim 7. Levardo discloses the semiconductor device according to claim 2, Levardo further discloses wherein the mold compound (mold type encapsulant 128, Para [ 0098]) and the at least one peak of the corrugated part of the clip forms a single planar surface (clip 100 comprises a clip body 108, Para [ 0069]).
Regarding claim 8. Levardo discloses the semiconductor device according to claim 2, Levardo further discloses wherein the lead frame and/or the clip are made of a conductive metal sheet (Para [ 0037, 0082]).
Regarding claim 10. Levardo discloses the semiconductor device according to claim 2, Levardo further discloses wherein the corrugated part of the clip comprises three or four peaks (clip 100 comprises a clip body 108, Para [ 0069]).
Allowable Subject Matter
Claims 4 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 5. The semiconductor device according to claim 1, wherein the clip is made of a metal sheet and has a width of 200 pm, and wherein the corrugated part has a width that is two times the width of the metal sheet.
Regarding claim 9. The semiconductor device according to claim 2, wherein the clip is made of a metal sheet and has a width of 200 pm, and wherein the corrugated part has a width that is two times width of the metal sheet.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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