Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election was made without traverse in the reply filed on 3/5/2026. Applicant has elected Group II, corresponding to claims 1-9. Invention Groups I and III, corresponding to 10-14 and 15, respectively, are withdrawn from further consideration.
Specification
The specification submitted 10/26/2023 has been accepted by the examiner.
Drawings
The drawings submitted on 10/26/2023 have been accepted by the examiner.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/26/2023 has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1-2, 4-6, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Pernel (US 20210193870 A1) in view of Tan (US 20220208848 A1).
Regarding Claim 1, Pernel teaches a growth substrate, suitable for epitaxial growth of an array of InGaN based diodes": (Pernel discloses a finished pseudo-substrate (200, Fig. 3C) adapted for the manufacture of a diode matrix; see [0084]);
an insulation lower layer made of a GaN based non-porous crystalline material": (Pernel teaches a first layer (202, Fig. 3C) of crystalline GaN, preferably unintentionally doped and non-porous, with a thickness between 1 and 4 microns; see also [0072], [0097]);
mesas M(i), made of GaN based crystalline materials, resting on and in contact with the insulation lower layer": (Pernel teaches mesas formed from etched portions of second layer 204, Fig. 3C made of crystalline GaN-based materials. Under a Broadest Reasonable Interpretation (BRI), these mesas are "in contact" with the insulation lower layer (202) as they are part of a continuous epitaxial stack; see also [0072], [0073]);
each mesa including N doped layers, with N>=2 (see Figs. 1-3), separated in pairs by an insulation intermediate layer (300) made of a non-porous material: (Pernel teaches an electrically insulating layer (300) that can be made of non-porous oxide or nitride, such as silicon oxide or silicon nitride; see also [0112]);
each having a free upper face adapted for making a diode of the array by epitaxy (Pernel teaches that the top of the mesa stack remains non-porous to serve as a template for subsequent epitaxy [0075], [0084]).
Although Pernel discloses much of the claimed invention, it does not explicitly teach configuring the mesas including
a category of mesas M(N) in which the N doped layers are porous;
a category of mesas M(o) in which none of the doped layers is porous;
a category of mesas M(n) in which n doped layers are porous, with 1sn<N.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
For example, Tan teaches that by selectively activating specific layers within a vertical stack during electrochemical processing, different regions of the same substrate can be rendered with different porosities and lattice constants to achieve specific emission colors ([0082], [0105]). Specifically, Tan teaches that the emission wavelength of the active layer may be changed according to the porosity of the underlying layer ([0105]). Tan further discloses a display device where individual sub-pixels emit different lights (blue, green, and red) by ensuring the porosities of the porous semiconductor layers in the first to third sub-pixels are "different from each other" ([0011], [0106]).
A person having ordinary skill in the art would have recognized that modifying the mesas of Pernel with the categories of mesas suggested by Tan would be obvious. Specifically, the modification suggested by Tan would be to employ a growth substrate with mesas configured according to at least three different categories including
a category of mesas M(N) in which the N doped layers are porous;
a category of mesas M(o) in which none of the doped layers is porous;
a category of mesas M(n) in which n doped layers are porous, with 1sn<N.
It would have been obvious for a person having ordinary skill in this art to modify the multi-mesa structure of Pernel to be structured according to the categorical porosification taught by Tan. A person of ordinary skill would be motivated to adopt this categorical approach to provide a single-chip solution for micro-LED displays where red, green, and blue diodes are grown simultaneously on the same substrate. By varying the electrochemical etching parameters for each mesa category (M(0), M(n), M(N)), a manufacturer can achieve the native growth of multiple emission wavelengths, significantly reducing the complexity of sub-pixel integration.
Regarding Claim 2, Pernel discloses at least one doped layer (204) and an insulating layer (300). Tan teaches a vertical stack of multiple doped layers (504, 506) designed for selective porosification. It would have been a matter of routine optimization for a person of ordinary skill in the art (PHOSITA) to select a specific number of layers ($N=2$ or $3$) based on the desired number of emission wavelengths (e.g., Green and Red) to be integrated on the substrate.
Regarding Claim 4, Pernel explicitly teaches the use of InGaN for the doped layers of the mesas to facilitate strain relaxation ([0053], [0074]). Thus, the material choice is directly anticipated.
Regarding Claim 5, Pernel teaches that the lower layer (202) is preferably unintentionally doped (uid) GaN ([0072]). It is well-known in the art of MOCVD growth that "uid" GaN inherently possesses a background carrier concentration within the claimed range. Furthermore, the intermediate layer (300) in Pernel is an oxide or nitride ([0112]), which are dielectrics with negligible doping levels.
Regarding Claim 6, Tan discloses "doped semiconductor layers" for porosification. It is standard functional practice in electrochemical etching to utilize n-type doping to facilitate the formation of the depletion region necessary for pore formation.
Regarding Claim 8 & 9, Pernel discloses an optoelectronic device matrix ([0013]). Tan teaches the specific application of a multi-layer porous stack to create a display device with blue, green, and red sub-pixels ([0106]). Combining the substrate of Pernel with the known RGB application of Tan yields a predictable result.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Pernel (US 20210133870 A1) in view of Tan (US 20220208848 A1) and further in view of Ali et al. (US 20230053213 A1).
Regarding Claim 7, Pernel discloses a growth substrate comprising mesas with at least one doped layer (204) and an insulating layer (300). Pernel teaches that the insulating layer serves as a mask or passivation during electrochemical etching ([0112], [0116]).
Tan teaches the concept of "Categorical" porosification, where different sub-pixels in an RGB array are formed by varying the porosity of a vertical stack of semiconductor layers ([0105-0106]).
It would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the mesa structure of Pernel to include the tiered, categorical porosification layers of Tan in order to achieve monolithic RGB integration on a single substrate.
Furthermore, Ali specifically addresses the epitaxial growth process for such multi-layer porous stacks. Ali teaches in paragraph [0052] that a "plurality of semiconductor layers" should be grown as a "single epitaxial growth process" across the entire substrate to form a common starting template for subsequent differential porosification ([0053]).
It would have been obvious to a person of ordinary skill in the art to implement the teaching of Ali by ensuring that the lower doped, intermediate, and upper doped layers of said mesas are of the same material and same thickness across all mesa categories (M(0), M(n), M(N)).
The motivation for this specific modification (the "Universal Template" of Claim 7) is manufacturing efficiency and process control. Growing the entire N-layer stack in a single, continuous epitaxial run—as taught by Ali [0052]—minimizes wafer handling, reduces thermal budget issues, and ensures that the "categorical" differences between red, green, and blue pixels are controlled entirely by the post-growth electrochemical etching parameters rather than complex, non-uniform epitaxial growth steps.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, although the prior art shows substantial features of the claimed invention, the prior art reviewed by the examiner neither teaches nor reasonably suggests all the claimed limitations, including a motivation to create a vertical series circuit within a single mesa. This configuration provides a unique technical advantage in driving high-voltage micro-LED arrays that is not suggested by the "individual sub-pixel" control taught in Tan.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached on normally working Monday-Friday between 9 am and 6 pm Pacific Time.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899