Prosecution Insights
Last updated: April 19, 2026
Application No. 18/495,128

HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME

Non-Final OA §103§112
Filed
Oct 26, 2023
Examiner
CAMPBELL, SHAUN M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan-Asia Semiconductor Corporation
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
81%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
742 granted / 1025 resolved
+4.4% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
47 currently pending
Career history
1072
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
53.2%
+13.2% vs TC avg
§102
26.5%
-13.5% vs TC avg
§112
14.3%
-25.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1025 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions Claims 8-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/19/2026. Claims 1-7 are elected for examination. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3 recites the limitation "the connection surface" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 4 recites the limitation "the connection surface" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kikkawa (US Pub. No. 2014/0091316 A1) in view of Endo et al. (US Pub. No. 2012/0056191 A1), hereafter referred to as Endo. As to claim 1, Kikkawa discloses a high electron mobility transistor (fig 7, [0033], [0035]), comprising: a substrate (110); a buffer layer (121) located on the substrate (110); a channel layer (122) located on the buffer layer (121); a first semiconductor epitaxial structure (123; [0033]) located on the channel layer (122) and including a supply layer ([0033]), and the first semiconductor epitaxial structure being formed with a hollow part (hollow middle part), and the hollow part extending from a top surface of the supply layer (123) toward the channel layer (122); a second semiconductor epitaxial structure (126/127) located in the hollow part (hollow part of 123) and sequentially including an aluminum gallium nitride layer (126; [0035]) and a P-type gallium nitride layer (127; [0033]); a drain (133) and a source (132) respectively arranged on the top surface of the supply layer (123); and a gate (131) arranged on a top surface of the P-type gallium nitride layer (127). Kikkawa does not disclose wherein the supply layer sequentially includes a first aluminum gallium nitride layer, a supply layer and a second aluminum gallium nitride layer. Nonetheless, Endo discloses a HEMT (fig 1, [0027]) including a supply layer that sequentially includes a first aluminum gallium nitride layer, a supply layer and a second aluminum gallium nitride layer (fig 1, supply layer 8 including layers 3/4/5; [0028]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the supply layer of Kikkawa with the three layer stack as taught by Endo since this will improve control of the depth of a recess in the layers above the channel region. As to claim 2, Kikkawa in view of Endo disclose the high electron mobility transistor of claim 1 (paragraphs above). Kikkawa further discloses wherein the top surface of the supply layer (123) of the first semiconductor epitaxial structure (123) and the top surface of the P-type gallium nitride layer (127) are not on the same plane. As to claim 3, Kikkawa in view of Endo disclose the high electron mobility transistor of claim 1 (paragraphs above). Kikkawa further discloses wherein the top surface of the supply layer of the first semiconductor epitaxial structure (123) and the connection surface between the aluminum gallium nitride layer and the P-type gallium nitride layer of the second semiconductor epitaxial structure are not on the same plane (surface between 126/127). As to claim 4, Kikkawa in view of Endo disclose the high electron mobility transistor of claim 1 (paragraphs above). Kikkawa further discloses wherein the connection surface between the aluminum gallium nitride layer (126) and the P-type gallium nitride layer (127) of the second semiconductor epitaxial structure is not higher than the top surface of the supply layer (123) of the first semiconductor epitaxial structure (123). As to claim 5, Kikkawa in view of Endo disclose the high electron mobility transistor of claim 1 (paragraphs above). Kikkawa further discloses wherein the supply layer is an N-type aluminum gallium nitride layer ([0040]). As to claim 6, Kikkawa in view of Endo disclose the high electron mobility transistor of claim 1 (paragraphs above). Kikkawa further discloses wherein a bottom surface of the hollow part is between the connection surface the supply layer (123; as supply layer is made of layer regions 3/4/5 as combined with Endo, above), and the connection surface of the lower layer of supply layer (123) and the channel layer (122). As to claim 7, Kikkawa in view of Endo disclose the high electron mobility transistor of claim 1 (paragraphs above). Kikkawa further discloses wherein the thickness of the aluminum gallium nitride layer of the second semiconductor epitaxial structure is from 10 nm to 50 nm ([0035]), and the thickness of the P-type gallium nitride layer is from 1 nm to 100 nm ([0035]). Pertinent Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2023/0197840A1; US 2023/0163207A1; US 2023/0015042A1. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 3/18/2026
Read full office action

Prosecution Timeline

Oct 26, 2023
Application Filed
Mar 18, 2026
Non-Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
81%
With Interview (+8.3%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 1025 resolved cases by this examiner. Grant probability derived from career allow rate.

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