DETAILED ACTION
This non-final action is responsive to communications: response dated 11/03/2025 and applicant-initiated interview dated 01/16/2026.
Applicant amended claims 1, 3, 4, 8-9, 11-13, 15, and 19-20; no claims are cancelled or none added. Claims 1-20 are pending. Claims 1, 9, and 14 are independent.
Finality of previous office action is being withdrawn
This non-final office action is responsive to the following communications: response dated 11/03/2025 and applicant-initiated interview dated 01/16/2026. See attached interview summary. Applicant’s arguments presented during interview of 01/16/2026 is persuasive. Applicant’s request for reconsideration of the finality of the rejection of the last Office action is persuasive and, therefore, the finality of that action is withdrawn. A new non-final office action is being issued. MPEP 706.07 (c)-(d).
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
8. Claims 1, 9, and 14 is/are rejected under 35 U.S.C. 103 as being obvious over Piccardi et al. (US 10,796,773 B1), in view of WANG et al. (US 2017 /0365335 A1).
Regarding independent claim 1, Piccardi teaches a nonvolatile memory device (Fig. 3: 300 NAND memory device), comprising:
a cell array (Fig. 3: 302 memory array) divided into a plurality of planes (Fig. 7: 304 “planes”; see col. 7, lines 6-12);
a voltage generator (Fig. 3: 308_0 to 308_N) configured to generate a plurality of word line voltages (col. 10, lines 20-34: 504, 514 “word line voltage”), each word line voltage of the plurality of word line voltages applied to word lines of each plane of the plurality of planes (col. 10, lines 20-34: 504 is applied to first plane, 514 is applied to second plane);
a row decoder configured to transmit the plurality of word line voltages to the cell array in response to an address (see col. 2, lines 65-67; Fig. 1: 108); and
a control circuit (Fig. 3: 318) configured to set up word line voltages of each of the plurality of planes to the word line voltage in response to an activated pseudo plane independent read mode setting (col. 8, lines 1-20: power modes to access and turn on word lines of first plane and second plane),
wherein the control circuit, in response to receiving a multi-plane command (col. 8, lines 1-20: “…a synchronous command…a command to access multiple planes of the memory array in parallel…”), is configured to sequentially shift voltage setup times of selected word lines by a specified time delay (Fig. 5A: 516) corresponding to a number of the plurality of planes (Fig. 5A in context of col. 10, lines 20-54: see 504 applied to first plane and after 514 is applied to second plane with 516 delay),
the selected word lines being word lines in planes of the plurality of planes (word lines in first plane and second plane, see Fig. 3, Fig. 2D),
the planes in the plurality of planes being selected by the multi-plane command (“synchronous command”, see col. 8, liens 25-32; col. 8, lines 1-20).
Piccardi is silent with respect to plane specific row recode: row decoder configured to transmit the plurality of word line voltages to the cell array in response to an address
WANG teaches plane specific row decoder further teaching -
row decoder (Fig. 2 and Fig. 7: 12A, 12B) configured to transmit the plurality of word line voltages to the cell array in response to an address (Fig. 2 and Fig. 7: word lines of planes plane <0>, plane <1>; para [0069]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the decoder circuitry of WANG into the apparatus of Piccardi such that claimed apparatus and functionality can be employed in order to improve read execution speed, read priority implementation in a multi-plane operation “…memory system capable of accelerating…operation….” (WANG para [0044]).
Regarding independent claim 9, a method for operating a nonvolatile memory device including a plurality of planes, the method comprising:
receiving a multi-plane input command;
determining whether a pseudo plane independent read mode is activated in response to the multi-plane input command; and
in response to determining that the pseudo plane independent read mode is activated and receiving the multi-plane input command, setting up a plurality of word line voltages of each plane of the plurality of planes to a specified word line voltage,
wherein voltage setup times of word lines are sequentially shifted by a specified time delay corresponding to a number of the plurality of planes.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1 over Piccardi and WANG).
Regarding independent claim 14, Piccardi teaches a nonvolatile memory device (Fig. 3: 300 NAND memory device) comprising:
a cell array (Fig. 3: 302 memory array) including a first plane and a second plane (Fig. 7: 304_0, 304_1 “planes”; see col. 7, lines 6-12);
a first plane row decoder configured to transmit a word line voltage to the first plane; a second plane row decoder configured to transmit the word line voltage to the second plane (see col. 2, lines 65-67; Fig. 1: 108); and
a control circuit (Fig. 3: 318. See col. 8, lines 1-20: power modes to access and turn on word lines of first plane and second plane) configured to set up voltages of word lines of the first plane and the second plane with the word line voltage at different points of time (Fig. 5A in context of col. 10, lines 20-54: see 504 applied to first plane and 514 is applied to second plane with 516 delay) in response to a multi-plane read command (col. 8, lines 1-20: “…a synchronous command…a command to access multiple planes of the memory array in parallel…”).
Piccardi is silent with respect to plane specific row recode: a first plane row decoder configured to transmit a word line voltage to the first plane; a second plane row decoder configured to transmit the word line voltage to the second plane
WANG teaches plane specific row decoder further teaching -
a first plane row decoder (Fig. 2 and Fig. 7: 12A) configured to transmit a word line voltage to the first plane (Fig. 2 and Fig. 7: plane <0>. See para [0069]);
a second plane row decoder (Fig. 2 and Fig. 7: 12B) configured to transmit the word line voltage to the second plane (Fig. 2 and Fig. 7: 12B. See para [0069])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the decoder circuitry of WANG into the apparatus of Piccardi such that claimed apparatus and functionality can be employed in order to improve read execution speed, read priority implementation in a multi-plane operation “…memory system capable of accelerating…operation….” (WANG para [0044]).
9. Claims 2-4, 7-8, 11-13, 15-16, and 20 is/are rejected under 35 U.S.C. 103 as being obvious over Piccardi et al. (US 10,796,773 B1), and WANG et al. (US 2017 /0365335 A1), in view of GUO (US 2022/0319571 A1).
Regarding claim 2, Piccardi and WANG teach the device of claim 1. They are silent with respect to remaining provisions of this claim.
Guo teaches the specified time delay corresponds to (corresponds to interpreted as a resulting relation or correlation) a cycle in which data sensed from one of the plurality of planes in a data input/output line is output (Fig. 7A in context of para [0094]: data out of PL1 is in the cycle t11-t2 which overlap with the delay gap).
GUO further teaches a nonvolatile memory device (Fig. 2: 104 memory device), comprising: a cell array (Fig. 2: 202 memory array, para [0059]) divided into a plurality of planes (Fig. 2 and para [0060]: planes); a voltage generator (Fig. 2: 210, 212 combined as voltage generator) configured to generate a word line voltage applied to word lines of each of the plurality of planes (para [0006], para [0079]: “word line biases”, see Fig. 7A: PL WL ramp); a row decoder configured to transmit the word line voltage to the cell array in response to an address (para [0059], Fig. 2: 208 “row decoder/word line driver” and function); and a control circuit (Fig. 2: 212 control logic) configured to set up voltages of word lines of each of the plurality of planes to the word line voltage (para [0018], para [0019]) in response to an activated pseudo plane independent read mode setting (see para [0089], para [0090]: in response to AMPI read operation mode and associated commands), wherein the control circuit is configured to sequentially shift voltage setup times (see Fig. 7A) of the word lines by a specified time delay (Fig. 7A: t11-t33 timing shift introduced by “trimmable delay” or “auto detection scheme of ramping completion” discussed in e.g., para [0087]) corresponding to a number of the plurality of planes (Fig. 7A in context of para [0090]: “PL1 WL ramp” starts at t11 and “PL2 WL ramp” starts at delayed time t33).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the circuitry of GUO into the apparatus of Piccardi and WANG such that claimed apparatus and functionality can be employed in order to improve command execution priority in multi-plane operation.
Regarding claim 3, Piccardi and WANG teach the device of claim 1. They are silent with respect to remaining provisions of this claim.
Guo teaches wherein the voltage generator comprises:
a charge pump (Fig. 5: 50-5n) configured to boost a power supply voltage (supplied to regulators) in response to an enable signal (Fig. 5: associated with plane) from the control circuit (para [0079]-para [0080]); and
a plurality of word line voltage generators (Fig. 5: 500-5nm) configured to generate the word line voltage (Fig. 5: Vbias) transmitted to each of the plurality of planes using the boosted power supply voltage (See Fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the circuitry of GUO into the apparatus of Piccardi and WANG such that claimed apparatus and functionality can be employed in order to improve operational speed.
Regarding claim 4, Piccardi, WANG, and GUO teaches the device of claim 3. GUO teaches wherein the row decoder comprises a plurality of plane unit row decoders configured to transfer the word line voltage to word lines of each of the plurality of planes in response to plane setup control signals received from the control circuit (para [0059], para [0065]: “plane-level commands” in combination with row decoders, column decoders).
Regarding claim 7, Piccardi, WANG teach the device of claim 1. They are silent with respect to remaining provisions of this claim.
GUO teaches further comprising: a page buffer circuit (Fig. 2: 204 “page buffer”) configured to control bit lines of each of the plurality of planes and sense stored data according to control of the control circuit (para [0059]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the circuitry of GUO into the apparatus of Piccardi and WANG such that claimed apparatus and functionality can be employed in order to improve operational speed.
Regarding claim 8, Piccardi, WANG teach the device of claim 1. They are silent with respect to remaining provisions of this claim. GUO teaches wherein the word line voltage includes a read voltage or a read pass voltage for sensing memory cells (para [0017]: read operation and associated read voltage).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the circuitry of GUO into the apparatus of Piccardi and WANG such that claimed apparatus and functionality can be employed in order to improve operational speed.
Regarding claim 11, the method of claim 9, wherein setting up voltages of word lines of each of the plurality of planes as specified word line voltages comprises:
generating the word line voltage using a charge pump;
generating a plurality of plane setup control signals that are sequentially activated according to the specified time delay in response to the input command; and
sequentially setting up voltages of word lines of each of the plurality of planes with the word line voltage according to the plurality of plane setup control signals.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 3, and is therefore rejected for the same reasons as claim 3 over Piccardi, WANG, and GUO)
Regarding claim 12, Piccardi, WANG and GUO teach the method of claim 11. GUO teaches wherein the word line voltage is sequentially switched to word lines of each of the plurality of planes (Fig. 7A: PL1 WL ramp, PL2 WL ramp) in response to each of the plurality of plane setup control signals (Fig. 7A: control signal associated with AMPI Read PL1, AMPI Read PL2).
Regarding claim 13, Piccardi, WANG and GUO teach the method of claim 11. GUO teaches wherein the word line voltage includes a read voltage or a read pass voltage of memory cells (para [0017]: read operation and associated read voltage).
Regarding claim 15, Piccardi, and WANG teach the device of claim 14. They are silent with respect to remaining provisions of this claim.
GUO teaches setting up voltages of word lines of the second plane occurs at a time shifted by a specified time delay after setting up voltages of word lines of the first plane (Fig. 7A in context of para [0090]: “PL1 WL ramp” starts at t11 and “PL2 WL ramp” starts at delayed time t33).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the circuitry of GUO into the apparatus of Piccardi and WANG such that claimed apparatus and functionality can be employed in order to improve operational speed.
Regarding claim 16, Piccardi, WANG, and GUO teaches the device of claim 15. GUO teaches wherein the specified time delay corresponds to a cycle in which data sensed in one of the first plane and the second plane is output to a data input/output line. (See claim 3 rejection analysis)
Regarding claim 20, Piccardi, and WANG teach the device of claim 14. They are silent with respect to remaining provisions of this claim. GUO teaches the device comprising: a voltage generator configured to generate the word line voltage using a charge pump (Fig. 7A and para [0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the circuitry of GUO into the apparatus of Piccardi and WANG such that claimed apparatus and functionality can be employed in order to improve operational speed.
Allowable Subject Matter
Claims 5-6, 10, and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 19, and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Piccardi (US 10,796,773 B1): Fig. 3-Fig.7E disclosure applicable for all claims. Huynh (US 9,698,676 B1): Fig. 3-Fig.7E disclosure applicable for all claims
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached at (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825