Prosecution Insights
Last updated: May 29, 2026
Application No. 18/495,246

STEM AND METHOD OF MANUFACTURING STEM

Non-Final OA §102
Filed
Oct 26, 2023
Priority
Nov 01, 2022 — JP 2022-175552
Examiner
ULLAH, ELIAS
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shinko Electric Industries Co. Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
709 granted / 838 resolved
+16.6% vs TC avg
Moderate +8% lift
Without
With
+8.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
14 currently pending
Career history
856
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.2%
+9.2% vs TC avg
§102
46.9%
+6.9% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 838 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Narita (US 2008/0054927). Regarding claims 1 and 7, Narita shows a stem (prove assembly 10 in FIG. 1 and [0032])) comprising: a base member (ring plate 58) that includes a main body portion (main body plate 58), and a columnar portion ( corner opening portion of substrate 12) that rises from one surface of the main body portion ( ring 52); and a block member that includes a device mounting surface, on which a semiconductor device ( device 68a as seen FIG. 7b) is able to be mounted, and that is fixed to the one surface of the main body portion in a state in which the block member is pressed against the columnar portion (see FIG. 1 with respect to FIG. 2-7). Regarding claim 2, Narita shows a stem (prove assembly 10 in FIG. 1 and [0032])) comprising, wherein the block member includes an area which is pressed (pressed by spring 28/14) against the columnar portion on a same surface side as a side of the device mounting surface ( element 50 as shown in FIG. 2) in a plan view of the main body portion viewed from the one surface (see FIG. 1 with respect to FIG. 2). Regarding claim 3, Narita shows a stem (prove assembly 10 in FIG. 1 and [0032])) comprising, wherein the block member includes an area which is pressed against the columnar portion on another surface side that is different from a side of the device mounting surface in a plan view of the main body portion viewed from the one surface (see Fig. 1 with respect to FIG. 2). Regarding claim 4, Narita shows a stem (prove assembly 10 in FIG. 1 and [0032])) comprising, wherein the block member includes a recess portion in an area which is pressed against the columnar portion (see FIG. 2 with respect to FIG. 1). Regarding claim 5, Narita shows a stem (prove assembly 10 in FIG. 1 and [0032])) comprising, wherein the base member includes a plurality of the columnar portions and the block member is fixed to the one surface of the main body portion in a state in which the block member is pressed against the plurality of the columnar portions (press by spring 28 in FIG. 1). Regarding claim 6, Narita shows a stem (prove assembly 10 in FIG. 1 and [0032])) comprising, wherein further includes a plurality of leads that are respectively fixed to a plurality of through-holes ( hole located 58 in Fig. 1) each of which passes through the main body portion in a thickness direction wherein the block member includes a projecting portion that projects in a direction intersecting a line segment that connects the leads that are disposed opposite the block member and that are adjacent each other from among the plurality of leads ( bolt 64) and the device mounting surface is formed at a tip of the projecting portion (see FIG. 1). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 26, 2023
Application Filed
Dec 28, 2025
Non-Final Rejection (signed) — §102
Feb 20, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12642152
POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING A POWER SEMICONDUCTOR MODULE ARRANGEMENT
3y 0m to grant Granted May 26, 2026
Patent 12642145
SEMICONDUCTOR PACKAGE
2y 8m to grant Granted May 26, 2026
Patent 12642124
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
2y 9m to grant Granted May 26, 2026
Patent 12635580
SEMICONDUCTOR PACKAGES
3y 1m to grant Granted May 19, 2026
Patent 12635551
CHIP PACKAGE STRUCTURE
2y 9m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+8.0%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 838 resolved cases by this examiner. Grant probability derived from career allowance rate.

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