Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 03/04/2026. Currently, claims 1-20 are pending in the application. Claims 14-20 have been withdrawn from consideration.
Election/Restrictions
Applicant's election without traverse of Group I and Species IA (Figures 3A-3C, 6B and 9C), claims 1-13, in the reply filed on 03/04/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5, 10 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwata et al (US 20190296012 A1) in view of Akaiwa et al (US 10256099 B1) as an evidence.
Regarding claim 1, Figures 1-13 of Iwata disclose a device structure, comprising:
a first field effect transistor (PMOS in 701 region, [0048]);
a second field effect transistor (NMOS in 702 region, [0048]); and
a local interconnect structure comprising:
a first semiconductor pillar structure (742P/744P, boron doped semiconductor, [0082]) contacting a top surface of an active region (732P/734P, [0082]) of the first field effect transistor;
a first metallic contact via structure (782P, [0087]) contacting a top surface of the first semiconductor pillar structure (742P/744P, boron doped semiconductor, [0082]);
a metallic structure (not shown in Figures 1-13 of Iwata for CMOS ( [0087] of Iwata) but required to have the connection to form the CMOS wherein the source of PMOS needs to be connected to the drain of the NMOS transistor as shown by a conductor 368/468 in Figure 19 of Akaiwa which is cited as an evidence here) of contacting a top surface of the first metallic contact via structure (782P, [0087]); and
a second metallic contact via structure (782N, [0087]) contacting a bottom surface of the metallic structure (not shown in Figures 1-13 of Iwata for CMOS ( [0087] of Iwata) but required to have the connection to form the CMOS wherein the source of PMOS needs to be connected to the drain of the NMOS transistor as shown by a conductor 368/468 in Figure 19 of Akaiwa which is as an evidence here) and electrically connected to an electrical node (drain) of the second field effect transistor (NMOS in region 702, right one in the Figures).
Regarding claim 3, Figures 1-13 of Iwata disclose that the device structure of claim 1, further comprising a gate-level dielectric layer (770+65, [0065] and [0070], broadest reasonable interpretation) laterally surrounding gate electrodes (752/754, [0051]) of the field effect transistors, wherein a top surface of the first metallic contact via structure (782P) and a top surface of the second metallic contact via structure (782N) are located within a horizontal plane including a topmost surface of the gate-level dielectric layer.
Regarding claim 5, Figures 1-13 of Iwata disclose that the device structure of claim 1, wherein the electrical node (drain of NMOS, right transistor in the Figures) of the second field effect transistor comprises an active region (drain, 734N) of the second field effect transistor.
Regarding claim 10, Figures 1-13 of Iwata disclose that the device structure of claim 1, wherein the metallic structure (not shown in Figures 1-13 of Iwata for CMOS ( [0087] of Iwata) but required to have the connection to form the CMOS wherein the source of PMOS needs to be connected to the drain of the NMOS transistor as shown by a conductor 368/468 in Figure 19 of Akaiwa which is cited as an evidence here) is in direct contact with a top surface of the second metallic contact via structure (PMOS and NMOS source and drain are connected using the metallic structure in a CMOS).
Regarding claim 12, Figures 1-13 of Iwata disclose that the device structure of claim 1, further comprising a three-dimensional memory array located over a substrate (8, [0088]) and comprising an alternating stack of insulating layers (132, [0091]) and electrically conductive layers (146) and a two-dimensional array of memory stack structures vertically extending through the alternating stack, wherein: each of the memory stack structures comprises a respective vertical semiconductor channel (60, [0157]) and a respective vertical stack of memory elements located at levels of the electrically conductive layers (146); and the field effect transistors (101 and 102, [0107]) comprise components of a peripheral circuit ([0093]), which is located on the substrate and is configured to control operation of the three-dimensional memory array ([0144]).
Regarding claim 13, Figures 1-13 of Iwata disclose that the device structure of claim 12, wherein: the alternating stack ([0091]) comprises stepped surfaces; a retro-stepped dielectric material portion overlies the stepped surfaces (165/265) of the alternating stack; and a metal interconnect structure (488, [0093]) comprising a metal via portion vertically extends through the retro-stepped dielectric material portion (165/265, [0091]) and contacts a top surface of the metallic structure.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 are rejected under 35 U.S.C. 103 as being obvious over Iwata et al (US 20190296012 A1) in view of Akaiwa et al (US 10256099 B1) as an evidence and further in view of NISHIKAWA et al (US 20160351709 A1).
Regarding claims 6-7, Figures 1-13 of Iwata does not teach that the device structure of claim 5, further comprising a second semiconductor pillar structure contacting a top surface of the active region (734N) of the second field effect transistor (right transistor in the Figures) and contacting a bottom surface of the second metallic contact via structure (782N), wherein: the first semiconductor pillar structure consists essentially of a first doped semiconductor material; and the second semiconductor pillar structure consists essentially of a second doped semiconductor material having a same semiconductor material composition as the first semiconductor pillar structure.
However, NISHIKAWA is a pertinent art which teaches a CMOS, NMOS and PMOS circuitry ([01020]-[0121]), wherein NISHIKAWA teaches that a PMOS or an NMOS transistor source/drain contacts having semiconductor pillar structure (6A/6B, epitaxial pillar, [0049]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Iwata with a second semiconductor pillar structure contacting a top surface of the active region (734N) of the second field effect transistor (right transistor in the Figures) and contacting a bottom surface of the second metallic contact via structure (782N), wherein: the first semiconductor pillar structure consists essentially of a first doped semiconductor material; and the second semiconductor pillar structure consists essentially of a second doped semiconductor material having a same semiconductor material composition as the first semiconductor pillar structure according to the teaching of NISHIKAWA in order to have an improved breakdown voltage and lower manufacturing cost ([0002] of NISHIKAWA).
Claims 8-9 are rejected under 35 U.S.C. 103 as being obvious over Iwata et al (US 20190296012 A1) in view of Akaiwa et al (US 10256099 B1) as an evidence.
Regarding claims 8-9, Figures 1-13 of Iwata does not teach that the device structure of claim 1, wherein the electrical node of the second field effect transistor comprises a gate electrode of the second field effect transistor, and the second metallic contact via structure contacts a top surface of the gate electrode of the second field effect transistor.
However, Figure 13 of Iwata teaches that a peripheral circuitry of a three-dimensional (3D) memory stack structures having CMOS circuitry, wherein a gate of a PMOS and a NMOS is connected in CMOS as can be seen from Figure 19 of Akaiwa.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use a connectivity as claimed in order to from various circuitry connection in a peripheral circuitry of a three-dimensional (3D) memory stack structures having CMOS consists of NMOS and PMOS.
Claim 11 is rejected under 35 U.S.C. 103 as being obvious over Iwata et al (US 20190296012 A1) in view of Akaiwa et al (US 10256099 B1) as an evidence, and further in view of Gilbert et al (US 20010044205 A1).
Regarding claim 11, Figures 1-13 of Iwata do not teach that the device structure of claim 10, wherein the metallic structure comprises a metallic line structure which comprises: a metallic barrier liner in contact with the top surface of the first metallic contact via structure and in contact with the top surface of the second metallic contact via structure; and a metallic material portion overlying the metallic barrier liner, wherein sidewalls of the metallic material portion are vertically coincident with sidewalls of the metallic barrier liner.
However, Gilbert is a pertinent art which teaches a method of forming planar conductive via and interconnecting structure ([0019]), wherein Figure 1 of Gilbert taches such structure with a metallic line structure (164) which comprises: a metallic barrier liner (162, [0036]) in contact with the top surface of a metallic contact via structure (150), wherein sidewalls of the metallic material portion (164) are vertically coincident with sidewalls of the metallic barrier liner (162).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Iwata, wherein the metallic structure comprises a metallic line structure which comprises: a metallic barrier liner in contact with the top surface of the first metallic contact via structure and in contact with the top surface of the second metallic contact via structure; and a metallic material portion overlying the metallic barrier liner, wherein sidewalls of the metallic material portion are vertically coincident with sidewalls of the metallic barrier liner according to the teaching of Gilbert in order to provide a barrier layer between interlayer dielectric and metal lines ([0036] of Gilbert).
Allowable Subject Matter
Claims 2 and 4 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, there is no prior art available nor obvious motivation to combine elements of prior art which teaches a device structure, comprising: “wherein: the first field effect transistor comprises a stack of a first gate dielectric, a first gate electrode, and a first gate cap dielectric; and a top surface of the first metallic contact via structure and a top surface of the second metallic contact via structure are located within a horizontal plane including a top surface of the first gate cap dielectric” in combination with the limitations of the claim it depends on.
Regarding claim 4, there is no prior art available nor obvious motivation to combine elements of prior art which teaches a device structure, comprising: “wherein: the first field effect transistor comprises a first gate electrode and a first gate cap dielectric that overlies the first gate electrode; and a top surface of the first gate cap dielectric is located within the horizontal plane” in combination with the limitations of the claim it depends on.
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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