Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to a restriction requirement mailed on 12/18/2025, the Applicant elected without traverse Group I encompassing claims 1-4 on 02/02/2026. Non-elected Group I encompassing claims 5-10 has been withdrawn from examination.
Currently, claims 1-10 are pending and the elected claims 1-4 are examined below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement (IDS)
Three information disclosure statements submitted on 10/26/2023 ("10-26-23 IDS"), 08/19/2024 (“08-19-24 IDS”) and 04/07/2025 (“04-07-25 IDS”) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the 10-26-23 IDS, 08-19-24 IDS and 04-07-25 IDS are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR MODULE HAVING SIGNAL ASSEMBLY IN FIRST AND SECOND MOLDING COMPOUND [[AND MANUFACTURING METHOD THEREOF]]
A. Prior-art rejections based on Lee
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2015/0103498 A1 to Lee et al. ("Lee").
Fig. 8B of Lee has been annotated to support the rejection below:
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Regarding independent claim 1, Lee teaches a semiconductor module (para [0123] - “For convenience of explanation, repeated descriptions thereof will be omitted and a difference between FIGS. 1A and 1B and FIGS. 8A and 8B will be mainly described.”) comprising:
a substrate 110 (para [0126] - “substrate 110”);
at least one chip 131 and/or 133 (para [0046] - “first and second semiconductor chips 131 and 133 arranged on the substrate 110”) disposed on the substrate 110 and electrically connected to the substrate 110;
at least one signal assembly 171 and/or 173 (para [0124] - “…the fifteenth and sixteenth housing units A61 and A62 may house third and fourth electrodes 171 and 173”) disposed on the substrate 110 in a normal direction of the substrate 110 and electrically connected to the substrate 110;
a first molding compound 160 (para [0133] - “encapsulation member 160”) disposed on the substrate 110, the first molding compound 160 at least covering the at least one chip 131 and/or 133 and having at least one opening A61 and/or A62, and the at least one opening A61 and/or A62 exposing the at least one signal assembly 171 and/or 173; and
a second molding compound Filler (para [0078] - “The fillers may partially or fully fill gaps between the first electrodes 141 and the encapsulation member 160 or gaps between the second electrodes 143 and the encapsulation member 160. The fillers may contact some of the sides of the first electrodes 141 or the second electrodes 143.”) disposed on the substrate 110 and filling the at least one opening A61 and/or A62, the second molding compound Filler located between the at least one signal assembly 171 and/or 173 and the first molding compound 160 and (partially) covering the at least one signal assembly 171 and/or 173, wherein at least one contact interface is formed between the second molding compound Filler and the first molding compound 160 (para [0078]).
Regarding claim 2, Lee teaches the at least one signal assembly 171 or 173 comprises:
at least one power semiconductor package signal connection element disposed on the substrate 110, wherein the first molding compound 160 exposes the at least one power semiconductor package signal connection element 174 or 176 (para [0126] - “One of the third electrodes 171 may be bonded to the first upper conductive pattern 113a disposed on the upper surface of the substrate 110 by the first bonding member 121 interposed therebetween and may include a socket member 174 and a pin member 175 inserted into the socket member 174 and having a fourth width w4 that is smaller than a third width w3.”; para [0134] - “One of the fourth electrode 173 may be bonded to the fifth upper conductive pattern 113e disposed on the upper surface of the substrate 110 by the first bonding member 121 interposed therebetween and may include a socket member 176 having a fifth width w5 and a pin member 177 inserted into the socket member 176 and having a sixth width w6 smaller than the fifth width w5. The socket member 176 and the pin member 177 of the fourth electrode 173 may be substantially the same as the socket member 174 and the pin member 175 of the third electrode 171 other than the widths in the X direction.”); and
at least one implanted signal pin 175 or 177 inserted into the at least one power semiconductor package signal connection element 174 or 176, wherein the second molding compound (partially) covers the at least one power semiconductor package signal connection element 174 or 176 and a portion of the at least one implanted signal pin 175 or 177.
Regarding claim 3, Lee teaches at least one connector 153 and/or 155 (para [0089] - “The second and third wiring member 153 and 155”) electrically connects the at least one chip 131 and/or 133 and the substrate 110.
Regarding claim 4, Lee teaches the substrate 110 that has an upper surfaced and a lower surface opposite to each other and comprises a plurality of pins 171, 173, each of the pins 171, 173 comprises an inner pin part 175 or 177 and an outer pin part 174 or 176 (para [0126] - “One of the third electrodes 171 may be bonded to the first upper conductive pattern 113a disposed on the upper surface of the substrate 110 by the first bonding member 121 interposed therebetween and may include a socket member 174 and a pin member 175 inserted into the socket member 174 and having a fourth width w4 that is smaller than a third width w3.”; para [0134] - “One of the fourth electrode 173 may be bonded to the fifth upper conductive pattern 113e disposed on the upper surface of the substrate 110 by the first bonding member 121 interposed therebetween and may include a socket member 176 having a fifth width w5 and a pin member 177 inserted into the socket member 176 and having a sixth width w6 smaller than the fifth width w5. The socket member 176 and the pin member 177 of the fourth electrode 173 may be substantially the same as the socket member 174 and the pin member 175 of the third electrode 171 other than the widths in the X direction.”), the first molding compound 160 covers the upper surface of the substrate 110 and the inner pin part 175 or 177 of each of the pins 171, 173, and the outer pin part 174 or 176 of the each of the pins 171, 173 protrudes out of the first molding compound 160.
B. Prior-art rejections based on Ha
Claim Rejections - 35 USC § 1022
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2015/0145123 A1 to Ha (“Ha”) (cited in the 08-19-24 IDS).
Fig. 1 of Ha has been provided to support the rejection below:
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Regarding independent claim 1, Ha teaches a semiconductor module (see Fig. 1) comprising:
a substrate 100 (para [0034] - “substrate 100”);
at least one chip 200 (para [0034] - “semiconductor devices 200”) disposed on the substrate 100 and electrically connected to the substrate 100;
at least one signal assembly 700 (para [0034] - “pins 700”) disposed on the substrate 100 in a normal direction of the substrate 100 and electrically connected to the substrate 100;
a first molding compound 400 (para [0034] - “molding part 400”) disposed on the substrate 100, the first molding compound 400 at least covering the at least one chip 200 and having at least one opening (occupied by insulating material 800), and the at least one opening exposing the at least one signal assembly 700; and
a second molding compound 800 (para [0059] - “an insulating material 800”) disposed on the substrate 100 and filling the at least one opening, the second molding compound 800 located between the at least one signal assembly 700 and the first molding compound 400 and (partially) covering the at least one signal assembly 700, wherein at least one contact interface is formed between the second molding compound 800 and the first molding compound 400 (see Fig. 1).
Regarding claim 3, Ha teaches at least one connector 201 (para [0042] - “wires 201”) that electrically connects the at least one chip 200 and the substrate 100.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2024/0404926 A1 to Chi et al.
Pub. No. US 2024/0071892 A1 to Kim et al.
Pub. No. US 2023/0178506 A1 to Morisada
Pub. No. US 2022/0108939 A1 to Minotti et al.
Pub. No. US 2010/0013086 A1 to Obiraki et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 15 February 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status
2 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status