Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement submitted on 10/27/2023 ("10-27-23 IDS") is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 10-27-23 IDS is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SCANNING SINGLE ELECTRON TRANSISTOR HAVING A PLUNGER GATE OVER FIN
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Section 2173.02.I. of the MPEP provides the following guidance on how pre-issuance claims under examination are construed differently than patented claims:
Patented claims are not given the broadest reasonable interpretation during court proceedings involving infringement and validity, and can be interpreted based on a fully developed prosecution record. While "absolute precision is unattainable" in patented claims, the definiteness requirement "mandates clarity." Nautilus, Inc. v. Biosig Instruments, Inc., 527 U.S. __, 134 S. Ct. 2120, 2129, 110 USPQ2d 1688, 1693 (2014). A court will not find a patented claim indefinite unless the claim interpreted in light of the specification and the prosecution history fails to "inform those skilled in the art about the scope of the invention with reasonable certainty." Id. at 1689.
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The Office does not interpret claims when examining patent applications in the same manner as the courts. In re Packard, 751 F.3d 1307, 1312, 110 USPQ2d 1785, 1788 (Fed. Cir. 2014); In re Morris, 127 F.3d 1048, 1054, 44 USPQ2d 1023, 1028 (Fed. Cir. 1997); In re Zletz, 893 F.2d 319, 321-22 (Fed. Cir. 1989). The Office construes claims by giving them their broadest reasonable interpretation during prosecution in an effort to establish a clear record of what the applicant intends to claim. Such claim construction during prosecution may effectively result in a lower threshold for ambiguity than a court's determination. Packard, 751 F.3d at 1323-24, 110 USPQ2d at 1796-97 (Plager, J., concurring). However, applicant has the ability to amend the claims during prosecution to ensure that the meaning of the language is clear and definite prior to issuance or provide a persuasive explanation (with evidence as necessary) that a person of ordinary skill in the art would not consider the claim language unclear. In re Buszard, 504 F.3d 1364, 1366 (Fed. Cir. 2007)( claims are given their broadest reasonable interpretation during prosecution "to facilitate sharpening and clarifying the claims at the application stage"); see also In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984); In re Zletz, 893 F.2d 319, 322, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989).
Here, the independent claim 1 is indefinite, because it is unclear what is meant by “source gate” and “drain gate” as these terms appear to be unconventional terms that have not been defined by the Applicant. It is unclear whether the “source gate” has dual function of providing for a source and acting as a gate or that the “source gate” is made of the same metal that the gate is made of but is on the source side of the transistor and does not function as a gate. Similarly, it is unclear whether the “drain gate” has dual function of providing for a drain and acting as a gate or that the “drain gate” is made of the same metal that the gate is made of but is on the drain side of the transistor and does not function as a gate.
Claims 2-7 are indefinite, because they depend from the indefinite claim 1.
Independent claim 8 is indefinite for the same reasons that the independent claim 1 is indefinite.
Claims 9-14 are indefinite, because they depend from the indefinite independent claim 8.
Independent 15 is indefinite for the same reasons that the independent claim 1 is indefinite.
Claims 16-20 are indefinite, because they depend from the indefinite independent claim 15.
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2024/0127098 A1 to Gonzalez-Zalba ("Gonzalez-Zalba").
Fig. 4B of Gonzalez has been annotated to support the rejection below:
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Regarding independent claim 1, Gonzalez-Zalba teaches a scanning single electron transistor (see Fig. 4B as annotated above; see also Fig. 6) comprising:
a fin 401 or 601 (para [0102] - “The nanowire 401 includes highly-doped regions 404 and an undoped region 405.”; para [0126] - “In FIG. 6, the device includes a substrate 600 comprising silicon. The device comprises a silicon fin 601 protruding from the substrate 600 to form a fin field-effect transistor, FinFET. In this example, the silicon substrate 600 has been etched to form the fin 601 protruding from the remainder of the substrate.”) formed over a substrate silicon substrate or 600 (para [0101] - “The semiconductor layer 307 is supported on a substrate such as a silicon substrate.”);
a source gate 416 (para [0102] - “a source electrode 416”) over a first portion P1 of the substrate silicon substrate or 600, the source gate 416 extending over a sidewall of the fin 401;
a drain gate 426 (para [0102] - “a drain electrode 426”) over a second portion P2 of the substrate silicon substrate or 600, the drain gate 426 extending over the sidewall of the fin 401; and
a plunger gate 414 and/or 424 (para [0104] - “The first and second metallic regions 414, 424 are electrically connected to respective gate electrodes (not shown) which are connected to an external voltage source. The voltage source can be used to apply a voltage to the first and second metallic regions 414, 424 such that a double quantum dot can be induced beneath the first and second metallic regions 414, 424 at the functional interface. “) over a third portion P3 of the substrate silicon substrate or 600, the plunger gate 414 and/or 424 extending over the sidewall of the fin 401, the plunger gate 414 and/or 424 between the source gate 416 and the drain gate 426;
wherein the plunger gate 414 and/or 424 is etched back (A limitation of “is etched back” is a process limitation so it does not structurally limit the claim. Nevertheless, the plunger gate has been recited such that a top most surface of the fin is exposed.) to expose a topmost surface of the fin 401 (see Fig. 4B showing exposed undoped region 405) such that a quantum dot formed in the fin is free from screening by metallic materials in the plunger gate 414 and/or 424 (para [0104] - “The voltage source can be used to apply a voltage to the first and second metallic regions 414, 424 such that a double quantum dot can be induced beneath the first and second metallic regions 414, 424 at the functional interface. “).
Regarding claim 2, Gonzalez-Zalba teaches a dielectric layer 603 (para [0126] - “A thin dielectric layer 603 comprising silicon dioxide is disposed on the fin 601. First and second metallic regions 614, 624 are arranged to overly the two edges of the fin 601.” The first and second metallic regions 614 and 624 in Fig. 6 correspond to the first and second metallic regions 414 and 424.) directly on the substrate silicon substrate or 600 and directly on the fin 401 or 601.
Regarding claim 3, Gonzalez-Zalba teaches the plunger gate 414 and/or 424, the source gate 416, and the drain gate 426 that are directly on the dielectric layer 603 (please compare Fig. 4 and Fig. 6).
Regarding claim 4, Gonzalez-Zalba teaches a portion of the dielectric layer 603 that is exposed on the topmost surface of the fin 401 or 601 (see compare Fig. 4 and Fig. 6).
Regarding claim 6, Gonzalez-Zalba teaches the fin 401 or 601 that comprises a base portion having a first width and a top portion having a second width less than the first width (please compare Fig. 4 and. Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
(1). Determining the scope and contents of the prior art.
(2). Ascertaining the differences between the prior art and the claims at issue.
(3). Resolving the level of ordinary skill in the pertinent art.
(4). Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Gonzalez-Zalba.
Regarding claim 5, Gonzalez-Zalba teaches the plunger gate 414 and/or 424, the source gate 416, and the drain gate 426 that are etched back from the topmost surface of the fin 401 or 601.
Gonzalez-Zalba does not specify the etched back of a height of 10 nanometers.
However, in Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Court held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04).
Since the only difference between the claimed transistor and the transistor taught by Gonzalez-Zalba is a relative dimension of the etched back of a height of 10 nanometers, the Court would be more likely than not hold that the claimed transistor is not patentably distinct from the transistor taught by Gonzalez-Zalba. Moreover, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art modify the transistor such that the etched back is a height of 10 nanometers with a reasonable expectation of providing a transistor that is in the nanometer scale as the one of ordinary skill in the semiconductor art is incentivized to make adjustments to size to fit an intended purpose of making device smaller as market forces demand that the device scale down with Moore's Law.
Regarding claim 7, Gonzalez-Zalba teaches the top portion having the second width.
Gonzalez-Zalba does not specify that the second width is less than 20 nanometers.
However, in Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Court held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04).
Since the only difference between the claimed transistor and the transistor taught by Gonzalez-Zalba is a relative dimension of the second width of being less than 20 nanometers, the Court would be more likely than not hold that the claimed transistor is not patentably distinct from the transistor taught by Gonzalez-Zalba. Moreover, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art modify the transistor such that the second width is less than 20 nanometers with a reasonable expectation of providing a transistor that is in the nanometer scale as the one of ordinary skill in the semiconductor art is incentivized to make adjustments to size to fit an intended purpose of making device smaller as market forces demand that the device scale down with Moore's Law.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Independent claim 8 is rejected but would be allowable if its pending 35 U.S.C. 112(b) rejection is successfully traversed.
Claims 9-14 are allowable because they depend from the allowable independent claim 8.
Independent claim 15 is rejected but would be allowable if its pending 35 U.S.C. 112(b) rejection is successfully traversed.
Claims 16-20 are allowable because they depend from the allowable independent claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Patent No. US 11,990,516 B1 to George et al.
Pub. No. US 2023/0217840 A1 to Patomaki et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano, can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2817
12 March 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status