DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/27/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 02/23/2026 is acknowledged.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected process, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/23/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 9-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2024/0136346 to Liu et al (hereinafter Liu).
Regarding Claim 1, Liu discloses a semiconductor structure comprising:
at least two layers of semiconductor devices (Fig. 3A, 310/314), wherein a first layer (310) of the semiconductor devices contacts a semiconductor substrate (308) and connects to a first frontside interconnect wiring (310), and
wherein a second layer (312) of the semiconductor devices connects to a second frontside interconnect wiring (314) and a backside power delivery network (336).
Regarding Claim 2, Liu discloses the semiconductor structure of Claim 1, wherein the first frontside interconnect wiring connects by one or more first metal plugs (328, Fig. 3A) in a first dielectric layer (320) to one or more second metal plugs (334) in a second dielectric layer (330), and wherein the second metal plugs electrically connect to a first super via (342) in the second frontside interconnect wiring.
Regarding Claim 3, Liu discloses the semiconductor structure of Claim 1, wherein the first layer of semiconductor devices (308) includes one or more trench devices (318) in at least a portion of the semiconductor substrate.
Regarding Claim 4, Liu discloses the semiconductor structure of Claim 3, wherein the one or more trench devices (318) in the at least the portion of the semiconductor substrate (308) includes a semiconductor device selected from the group composed of an active semiconductor device and passive semiconductor device [0048].
Regarding Claim 5, Liu discloses the semiconductor structure of Claim 3, wherein the one or more trench devices (318) include an embedded random-access memory device [0048].
Regarding Claim 6, Liu discloses the semiconductor structure of Claim 2 wherein the first super via (342) connects to the second layer of semiconductor devices (312) by one or more contacts (332) contacting a first metal layer [0063].
Regarding Claim 9, Liu discloses a semiconductor structure comprising:
a semiconductor substrate (Fig. 3A, 308) with a first plurality of semiconductor devices (318; [0048]);
a first frontside interconnect wiring (310) connecting by one or more first contacts (322) to the first plurality of semiconductor devices (318);
a second bond layer electrically connecting with a first bond layer (306; “one or more bonding films”; [0049]);
a second frontside interconnect wiring (314) connecting the second bond layer (306, Fig. 3A) and the one or more first contacts (322) to a second plurality of semiconductor devices (316); and
a plurality of backside contacts (342) connecting the second plurality of semiconductor devices to a backside power delivery network (336).
Regarding Claim 10, Liu discloses the semiconductor structure of Claim 9, wherein the first plurality of semiconductor devices directly contacting the semiconductor substrate further comprises:
at least one semiconductor device (318) in a portion of the semiconductor substrate (308); and
the second plurality of semiconductor devices (316) are each directly contacting one of the plurality of backside contacts (342) and a backside dielectric layer (SOI; [0051]).
Regarding Claim 11, Liu discloses the semiconductor structure of Claim 9, wherein the first bond layer (306) includes at least one first metal plug (328) in a first oxide layer ([0049]; Examiner considers “one or more passivation layers” or “one or more layers of another type” to anticipate an oxide layer).
Regarding Claim 12, Liu discloses the semiconductor structure of Claim 11, wherein the second bond layer (306) includes at least one second metal plug (334) in a second oxide layer [0049], and wherein the at least one second metal plug and the at least one first metal plug (328) are electrically connected [0059].
Regarding Claim 13, Liu discloses the semiconductor structure of Claim 10, wherein the at least one semiconductor device (318) residing in the portion of the semiconductor substrate (308) is a deep trench decoupling capacitor [0070].
Regarding Claim 14, Liu discloses the semiconductor structure of Claim 10, wherein the at least one semiconductor device residing in the portion of the semiconductor substrate (302) is an embedded random-access memory devices [0048].
Regarding Claim 15, Liu discloses the semiconductor structure of Claim 9, wherein the first plurality of semiconductor devices includes at least one finFET device ([0048]; Examiner considers “a NAND die” to anticipate a finFET device as it is one type of gate used in NAND circuits).
Regarding Claim 16, Liu discloses the semiconductor structure of Claim 10, wherein each of the second plurality of semiconductor devices (316) reside between two isolation trenches on the at least a portion of the backside dielectric layer ([0079]; “one or more shallow trench isolation”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to Claim 3 above, and further in view of US PG Pub 2024/0421027 to Tong et al (hereinafter Tong).
Regarding Claims 7 and 8, Liu discloses the semiconductor structure of Claim 2, further comprising:
the one or more second metal plugs (334) in the second dielectric layer (330) contacting the one or more first metal plugs (328) in the first dielectric layer (320);
one or more second super vias ([0055; Examiner considers “pillars” “and/or another type of metallization layers” to anticipate one or more second super vias) connecting the one or more first metal plugs (328) to the semiconductor substrate (308).
Liu does not disclose one or more thermal contacts contacting the backside power delivery, one or more of the first super vias contacting the one or more thermal contacts or a cooling plate connected to the semiconductor substrate by at least a thermal interface material.
Tong discloses stacked semiconductor layers having, on a backside, thermal vias (256, Fig. 28A; [0171]) and a cooling plate (910) connected by a thermal interface material (282) to a semiconductor substrate (252).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the semiconductor structure of Liu to have included thermal vias and a cooling plate as these were common structures, known in the art, for dissipating heat generated by semiconductor devices. Having stacked semiconductor devices can cause an increase in heat generation due, at a minimum, to a reduction in external surfaces for dissipation and an increased density and proximity of devices generating heat. Utilizing thermal vias and cooling plates would have been an obvious design choice.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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