Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4,6,7,9-15,17,18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato et al. (US-20070210866-A1; Sato).
Regarding claim 1, Sato discloses an electronic device, comprising: a substrate (Fig. 10, 3; ¶100) defining a first face and a second face opposite to each other; a thin film layer (Fig. 10, 12/14; ¶100) formed on the first face of the substrate; one or more passive elements (Fig. 10, 5/6; ¶100) arranged on the first face of the substrate or the thin film layer and electrically connecting to the thin film layer; and one or more semiconductor chips (Fig. 10, 2 /4; ¶100) are disposed on the first face of the substrate or on the thin film layer, and electrically connecting to the thin film layer; wherein one or ones of the semiconductor chips define an operating frequency not less than 1 GHz (1.8GHz).
Regarding claim 2, Sato discloses the electronic device as claimed in claim 1, wherein one or ones of the passive elements (Fig. 10, 5/6; ¶100) are integrally made of the thin film layer. (Fig. 10, 12/14; ¶100)
Claim 1 claims the passive element is arranged on the substrate or the thin film layer and electrically connected to the thin film layer. The language means that passive element is not integral with the thin film layer but attached or coupled to it as a separate element. Claim 2 will be interpreted to be consistent with the language of claim 1, where when the passive element is attached or electrically coupled to the thin film layer makes it is integral.
Regarding claim 3, Sato discloses the electronic device as claimed in claim 1, wherein the passive element (Fig. 10, 5/6; ¶100) includes at least one of a resistor, an inductor, a capacitor (clear from figure), a coupler, a microstrip, or an impedance matching unit.
Regarding claim 4, Sato discloses the electronic device as claimed in claim 1, wherein one or ones of the passive elements (Fig. 10, 5/6; ¶100) are individually disposed thereon.
Regarding claim 6, Sato discloses the electronic device as claimed in claim 1, wherein the substrate defines a dissipation factor is not greater than 0.01.(¶101)
Sato does not specifically state that the substrate has a dissipation factor of not greater than 0.01.
However, applicant discloses the substrate is made of glass. Sato discloses substrate (Fig. 10, 3; ¶100) is also made of glass (¶101 a glass epoxy resin). Since Sato and applicant use glass for the substrate it is concluded that Sato’s substrate also comprises the claimed heat dissipation characteristics of not greater than 0.01
Regarding claim 7, Sato discloses the electronic device as claimed in claim 1, wherein the substrate is an insulating substrate. (Fig. 10, 3; ¶101)
Regarding claim 9, Sato discloses the electronic device as claimed in claim 1, wherein material(s) of one or ones of the semiconductor chips defines a band gap no less than 1 electron volt.
Sato discloses semiconductor chip 2 silicon based (¶106-107) and semiconductor chip 4 is GaAs (¶117). Applicant discloses the band gap is no less than 1.1 eV when the material(s) of the semiconductor chip(s) is selected as Silicon, and the band gap is no less than 1.4 eV when the material(s) of the semiconductor chip(s) is selected as III-V compound. GaAs is a III-V compound. Therefore, since Sato discloses the same materials as applicant it is concluded that Sato also discloses the claimed material characteristics, that is a band gap no less than 1.1 eV.
Regarding claim 10, Sato discloses the electronic device as claimed in claim 1, wherein one or ones of the semiconductor chips (Fig. 10, 2 /4; ¶100) are one or more epitaxial structures lift-off from an original wafer.
This claim represents a product by process. The presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.
Regarding claim 11, Sato discloses the electronic device as claimed in claim 10, wherein the original wafer is made of materials of Gallium Nitride (GaN), Silicon Carbide (SiC), Sapphire, Gallium Arsenide (GaAs) (Fig. 10, 2 /4; ¶100,117), Silicon (Si), or Indium phosphide (InP).
Semiconductor chip 4 is a GaAs (¶117) material therefore the wafer substrate would have been GaAs.
Regarding claim 12, Sato discloses the electronic device as claimed in claim 1, wherein one or ones of the semiconductor chips (Fig. 10, 2 /4; ¶100) is compound semiconductors applied to radio frequency (RF) range.
Regarding claim 13, Sato discloses the electronic device as claimed in claim 1, wherein the thin film layer (Fig. 10, 12/14; ¶100) further defines a feeding line.
Regarding claim 14, Sato discloses the electronic device as claimed in claim 1, further including a first conductive layer (Fig. 10, 12d; ¶103) formed on the second face of the substrate. (Fig. 10, 3; ¶100)
Regarding claim 15, Sato discloses the electronic device as claimed in claim 14, wherein the (first) conductive layer (Fig. 10, 12d; ¶103) is a grounding or a common layer (common to a large portion of wiring not illustrated).
Regarding claim 17, Sato discloses the electronic device as claimed in claim 16, the first conductive layer (Fig. 10, 12d; ¶103) fully covers one or ones of the semiconductor chips (Fig. 10, 2 /4; ¶100) in a projection direction perpendicular to the substrate. (Fig. 10, 3; ¶100)
Regarding claim 18, Sato discloses the electronic device as claimed in claim 1, wherein one or ones of the semiconductor chips (Fig. 10, 2 /4; ¶100) include(s) transistor(s), diode(s), (Fig. 1, 2/4; ¶) or varactor(s), or any combination thereof.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US-20070210866-A1; Sato) in view of Tsai et al. (US-20200328166-A1; Tsai).
Regarding claim 5, Sato discloses the electronic device as claimed in claim 1, but is silent on the operating frequency of one or ones of the semiconductor chips is not less than 10 GHz.
Tsai discloses a semiconductor device comprising a semiconductor device and a passive component on a first surface of a substrate where the semiconductor chip operates at a frequency of 60 GHz (Fig. 2a, 21; ¶37)
Before the effective filing date of the invention, it would have been obvious to one having ordinary skill in the art for the semiconductor device to operate at 60GHz for creating a 5G device.
Claim(s) 8,16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US-20070210866-A1; Sato) in view of Tsvelykh et al. (US-10056922-B1; Tsvelykh).
Regarding claim 8, Sato discloses the electronic device as claimed in claim 1, but is silent on wherein the thin film layer (Fig. 10, 12/14; ¶100) includes a layer of thin metallic foil.
Tsvelykh discloses a radio frequency device comprising a radio frequency device on a thin film metal foil (Fig. 3, 30; column 12 lines 20-25)
Before the effective filing date of the invention, it would have been obvious to one having ordinary skill in the art to form the thin film layer of metal foil to simply the manufacturing process.
Regarding claim 16, Sato discloses the electronic device as claimed in claim 14, but is silent on wherein the first conductive layer is a patch antenna.
Tsvelykh discloses a radio frequency device comprising a conductive layer on the second side of a substrate formed as a patch antenna. (Fig. 3, 40; column 14 lines 20-25)
Before the effective filing date of the invention, it would have been obvious to one having ordinary skill in the art to make the antenna layer a patch antenna for use in mobile communications.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hatori et al. (US-20060057793-A1; Hatori) in view of Sato et al. (US-20070210866-A1; Sato).
Regarding claim 19, Hatori discloses an electronic apparatus comprising: a board (Fig. 3, 151; ¶78) defining a third conductive layer (Fig. 3, wiring not shown; ¶78); one or ones of the electronic devices (Fig. 3, 1; ¶78) …; and a plural of second conductors (Fig. 3, 153; ¶78) electrically connecting the board and one or ones of the electronic device.
Hatori discloses a power module comprising a passive device and semiconductor device analogous to claim 1. However, Hatori is silent on the comprising the one or more devices of claim 1. Sato discloses the claimed electronic device (Fig. 10, 1; ¶100) of claim 1.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill the art to incorporate the electronic device of Sato for making an improved power module device for mobile communication.
Regarding claim 20, Hatori in view of Sato discloses the electronic apparatus as claimed in claim 19, wherein the electronic device (Fig. 2, 1; ¶78 Hatori) includes a first conductive layer (Fig. 2, 12cb ¶72 Hatori) formed on the second face (bottom) of the substrate (Fig. 3, 3; ¶78 Hatori), and the conductive layer fully covers one or ones of the semiconductor chips (Fig. 3, 2; ¶78 Hatori) in a projection direction perpendicular to the substrate.
Conclusion
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899