DETAILED ACTION
This Office Action is in response to the application filed on 27 October 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2014/0264611 A1; hereinafter Lee), in view of Pruitt (US 2011/0298114 A1; hereinafter Pruitt).
In regards to claim 1, Lee teaches a semiconductor device (10) [0030], comprising:
a first semiconductor die (48) including a first surface (52) and a second surface (50) opposite the first surface [0030-0031], the first semiconductor die including a first active device (e.g. transistor as implied by source/drain contacts (54/58)) formed therein, the first active device comprising a first terminal (58) on the first surface and a second terminal (54) on the second surface (figs. 2-3) [0031];
a second semiconductor die (78) including a third surface (82) and a fourth (80) surface opposite the third surface [0033], the second semiconductor die including a second active device (e.g. transistor as implied by source/drain contacts (84/88)) formed therein, the second active device comprising a third terminal (88) on the third surface and a fourth terminal (84) on the fourth surface (fig. 4) [0033];
a first interconnect layer (60) between the first surface and the fourth surface, the first interconnect layer configured to provide vertical separation (e.g. by the stack depicted in fig. 5) between the first and second semiconductor dies and to provide electrical connection between the first terminal and the fourth terminal (figs. 4-5; [0032]: "… bonded or connected to semiconductor chip 48 through a layer of an electrically conductive material 60…."); and
a conductive element (92) having a first end (93) electrically connected to the third surface,
wherein the second surface of the first semiconductor die is electrically connected to a first leadframe (20), and a second end (94) of the conductive element is electrically connected to a second leadframe (26) (figs. 4-5; [0030-0033]).
Lee appears to be silent as to, but does not preclude, the limitations wherein the first and second semiconductor dies are sequentially stacked in a vertical direction on the first leadframe, a back surface of each of the first and second semiconductor dies facing a same direction. Pruitt teaches, e.g. in fig. 4, the limitations wherein the first (48) and second (78) semiconductor dies are sequentially stacked in a vertical direction on the first leadframe (20) (fig. 4: (78) is stacked on (48) which is stacked on (20)), a back surface (figs. 3-4: e.g. surfaces (50) and (80) respectively of (48) and (78) are rear surfaces) of each of the first and second semiconductor dies facing a same direction ((50) and (80) both face a "downwards" direction). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lee with the aforementioned limitations taught by Pruitt to minimize package size while optimizing heat dissipation (Pruitt [0006]).
In regards to claim 2, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 1. Lee further teaches the limitations further comprising a first electrical connection layer (55) between the first leadframe (20) and the second surface (50) the first semiconductor die (48), the first semiconductor die being attached to the first leadframe via the first electrical connection layer (figs. 3, 5; [0031]: e.g. solder, electrically conductive paste, conductive film, etc.).
In regards to claim 3, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 2. Lee further teaches the limitations further comprising a second electrical connection layer (85) between the first surface (52) of the first semiconductor die (48) and the fourth surface (80) of the second semiconductor die (78), the first semiconductor die being attached to the second semiconductor die via the second electrical connection layer (fig. 5; [0033]).
In regards to claim 4, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 3. Lee further teaches the limitations wherein each of the first and second electrical connection layers (55/85) comprises at least one of solder, conductive epoxy, or sintered metal material (figs. 3, 5; [0031], [0033]: e.g. solder, electrically conductive paste, conductive film, etc.).
In regards to claim 5, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 1. Lee further teaches the limitations wherein the conductive element (92) comprises a bond wire (fig. 5; [0033]).
In regards to claim 6, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 1. Lee further teaches the limitations wherein the conductive element (92) comprises a conductive clip (fig. 5; [0033]).
In regards to claim 7, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 6. Lee further teaches the limitations further comprising:
a first electrical connection layer (97) between a first end of the conductive clip (92) and the third surface (82) of the second semiconductor die (78) (fig. 5; [0033]); and
a second electrical connection layer (96) between a second end of the conductive clip and the second leadframe (26) (fig. 5; [0033]),
wherein the first end of the conductive clip is attached to the second semiconductor die via the first electrical connection layer, and the second end of the conductive clip is attached to the second leadframe via the second electrical connection layer (fig. 5; [0033]).
In regards to claim 8, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 1. Lee further teaches the limitations further comprising:
a first conductive material layer (54) on the second surface (50) of the first semiconductor die (48); and
a second conductive material layer (84) on the fourth surface (80) of the second semiconductor die (78),
wherein the first conductive material layer comprises the second terminal of the first active device, and the second conductive material layer comprises the fourth terminal of the second active device (figs. 2-4; [0031-0033]).
In regards to claim 9, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 1. Lee further teaches the limitations wherein the first (20) and second leadframes (26) are configured as laterally spaced portions of a common leadframe (14) of the semiconductor device (figs. 4-5; [0030], [0032]).
In regards to claim 10, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 1. Lee further teaches the limitations further comprising:
a second interconnect layer (55) between the second surface (50) of the first semiconductor die (48) and the first leadframe (20),
wherein the second interconnect layer is configured to provide vertical separation (e.g. by the stack depicted in fig. 5) between the first semiconductor die and the first leadframe and to provide electrical connection between the second terminal (54) and the first leadframe (fig. 5; [0031]).
In regards to claim 11, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 10. Lee further teaches the limitations wherein each of the first (60) and second (55) interconnect layers comprises at least one of: one or more conductive standoffs, one or more patterned metal structures, and one or more solder bumps (fig. 5; [0031-0033]).
In regards to claim 12, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 1. Lee further teaches the limitations wherein the first surface (52) is an upper surface of the first semiconductor die (48), the second surface (50) is a bottom surface of the first semiconductor die, the third surface (82) is an upper surface of the second semiconductor die (78), and the fourth surface (80) is a bottom surface of the second semiconductor die (fig. 5).
In regards to claim 13, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 1. Lee further teaches the limitations wherein the first surface (52) is a bottom surface of the first semiconductor die (48), the second surface is an upper surface (50) of the first semiconductor die, the third surface (82) is a bottom surface of the second semiconductor die (78), and the fourth surface (80) is an upper surface of the second semiconductor die (fig. 5: "upper" corresponding to the bottom of fig. 5 and "lower" corresponding to the top of fig. 5, "upper" and "lower" are relative terminology dependent on the viewpoint of an observer and there is no claimed reference frame to distinguish "upper" and "lower", therefore fig.5 may be viewed upside down with element (20) as the uppermost element).
In regards to claim 25, Lee teaches a method of fabricating a semiconductor device including at least first and second series-connected semiconductor dies (48/78) (figs. 4-5; abstract), the method comprising:
providing a first semiconductor die (48) including a first surface (52) and a second surface (50) opposite the first surface, the first semiconductor die including a first active device (e.g. transistor as implied by source/drain contacts (54/58)) formed therein, the first active device comprising a first terminal (58) on the first surface and a second terminal (54) on the second surface (figs. 2-3; [0031]);
electrically connecting the second surface of the first semiconductor die to a first leadframe of the semiconductor device (figs. 4-5; [0030]);
providing a second semiconductor die (78) including a third surface (82) and a fourth surface (80) opposite the third surface, the second semiconductor die including a second active device (e.g. transistor as implied by source/drain contacts (84/88)) formed therein, the second active device comprising a third terminal (88) on the third surface and a fourth terminal (82) on the fourth surface (fig. 4; [0033]);
forming a first interconnect layer (60) between the first surface of the first semiconductor die and the fourth surface of the second semiconductor die, the first interconnect layer being configured to provide vertical separation (e.g. implied by the stack depicted in fig. 5) between the first and second semiconductor dies and to provide electrical connection between the first terminal of the first active device and the fourth terminal of the second active device (figs. 4-5; [0032]); and
forming a conductive element (92) having a first end (93) electrically connected to the third surface of the second semiconductor die and having a second end electrically connected to a second leadframe (26) of the semiconductor device (figs. 4-5; [0032-0033]).
Lee appears to be silent as to, but does not preclude, the limitations wherein the first and second semiconductor dies are sequentially stacked in a vertical direction on the first leadframe, a back surface of each of the first and second semiconductor dies facing a same direction. Pruitt teaches, e.g. in fig. 4, the limitations wherein the first (48) and second (78) semiconductor dies are sequentially stacked in a vertical direction on the first leadframe (20) (fig. 4: (78) is stacked on (48) which is stacked on (20)), a back surface (figs. 3-4: e.g. surfaces (50) and (80) respectively of (48) and (78) are rear surfaces) of each of the first and second semiconductor dies facing a same direction ((50) and (80) both face a "downwards" direction). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lee with the aforementioned limitations taught by Pruitt to minimize package size while optimizing heat dissipation (Pruitt [0006]).
Claim(s) 27 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lee and Pruitt as applied to claim1 above, and further in view of Cho et al. (US 10,840,169 B2; hereinafter Cho).
In regards to claim 27, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 1. The combination of Lee and Pruitt appears to be silent as to, but does not preclude, the limitations wherein the first interconnect layer is configured to provide a non-planar surface between the first and second semiconductor dies in the vertical direction. Cho teaches the limitations wherein the first interconnect layer is configured to provide a non-planar surface between the first and second semiconductor dies in the vertical direction (fig. 2F: interconnect posts (121) have a non-planar surface) (col. 7/lns. 8-23). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Pruitt with the aforementioned limitations taught by Cho to have a cheaper, more reliable, smaller semiconductor package (Cho col. 1/lns. 13-16).
In regards to claim 28, the combination of Lee and Pruitt teaches the limitations discussed above in addressing claim 1. The combination of Lee and Pruitt appears to be silent as to, but does not preclude, the limitations wherein the first interconnect layer comprises a plurality of conductive standoffs spaced laterally from each other, and wherein the semiconductor device further comprises an insulating layer between adjacent conductive standoffs among the plurality of conductive standoffs. Cho teaches the limitations wherein the first interconnect layer comprises a plurality of conductive standoffs spaced laterally from each other, and wherein the semiconductor device further comprises an insulating layer between adjacent conductive standoffs among the plurality of conductive standoffs (fig. 2F: standoff interconnect posts (121) have a non-planar surface) (col. 7/lns. 8-23). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Lee and Pruitt with the aforementioned limitations taught by Cho to have a cheaper, more reliable, smaller semiconductor package (Cho col. 1/lns. 13-16).
Claim(s) 14-17, 19, 20-23, and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Zhou (US 2021/0327791 A1; hereinafter Zhou).
In regards to claim 14, Lee teaches a semiconductor device (fig. 19; abstract), comprising:
a first semiconductor die (48) including a first active device (e.g. transistor as implied by source/drain contacts (54/58)) formed therein, the first semiconductor die comprising a first upper surface (52) and a first bottom surface (50) opposite the first upper surface, the first semiconductor die electrically connected to a first leadframe (264) and configured such that the first bottom surface faces the first leadframe (fig. 3; [0031], [0050]);
a second semiconductor die (78) spaced laterally from the first semiconductor die and including a second active device formed therein (e.g. transistor as implied by source/drain contacts (84/88)), the second semiconductor die comprising a second upper surface (82) and a second bottom surface (80) opposite the second upper surface, the second semiconductor die electrically connected to a second leadframe (270) and configured such that the second upper surface faces the second leadframe (fig. 19: [0033], [0050]);
a conductive element (fig. 19: e.g. (276) of (270) in contact with (48/78)) electrically connecting the first (48) and second (78) semiconductor dies (fig. 19; [0053]);
a first interconnect layer (portions of (65) over (48)) between the first upper surface (52) and a first end of the conductive element (276), the first interconnect layer configured to provide vertical separation (e.g. shown by stack depicted in fig. 5) and electrical connection between the first semiconductor die and the conductive element (fig. 19; [0053]); and
a second interconnect layer (e.g. portions of (65) over (78)) between the second upper surface and the second leadframe, the second interconnect layer configured to provide vertical separation and electrical connection between the second semiconductor die and the second leadframe (fig. 19; [0053]).
Lee appears to be silent as to, but does not preclude, the limitations a conductive element electrically connecting the first and second semiconductor dies the conductive element being electrically disconnected from any leadframe. Zhou teaches the limitations a conductive element electrically connecting the first and second semiconductor dies the conductive element being electrically disconnected from any leadframe (fig. 1C: e.g. chip (102) is directly bonded to (120) by a middle conductive layer (118) which is not directly electrically connected to a leadframe, i.e. there are intermediate elements between (118) and a leadframe). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lee with the aforementioned limitations taught by Chou to have a compact, lower-inductance chip-on-chip arrangement (Chou Title).
In regards to claim 15, the combination of Lee and Chou teaches the limitations discussed above in addressing claim 14. Lee further teaches the limitations further comprising a first electrical connection layer (55) between the first leadframe (264) and the first bottom surface (50) the first semiconductor die (48), the first semiconductor die being attached to the first leadframe via the first electrical connection layer (fig. 19; [0051]).
In regards to claim 16, the combination of Lee and Chou teaches the limitations discussed above in addressing claim 15. Lee further teaches the limitations further comprising a second electrical connection layer (e.g. one of (65)) between the second upper surface (82) of the second semiconductor die (78) and the second leadframe (270), the second semiconductor die being attached to the second leadframe via the second electrical connection layer (fig. 19; [0053]).
In regards to claim 17, the combination of Lee and Chou teaches the limitations discussed above in addressing claim 16. Lee further teaches the limitations wherein each of the first (55) and second (65) electrical connection layers comprises at least one solder, conductive epoxy, or sintered metal material (fig. 19; [0051-0053]).
In regards to claim 19, the combination of Lee and Chou teaches the limitations discussed above in addressing claim 14. Lee further teaches the limitations wherein the conductive element (fig. 19: e.g. (276) of (270) in contact with (48/78)) comprises a conductive clip [0053].
In regards to claim 20, the combination of Lee and Chou teaches the limitations discussed above in addressing claim 19. Lee further teaches the limitations further comprising:
a first electrical connection layer (e.g. portions of (65)) between a first end of the conductive clip (270) and the first upper surface (52) of the first semiconductor die (48); and
a second electrical connection layer (e.g. other portions of (65)) between a second end of the conductive clip (276) and the second surface (84) of the second semiconductor die (78),
wherein the first end of the conductive clip is attached to the first semiconductor die via the first electrical connection layer, and the second end of the conductive clip is attached to the second semiconductor die via the second electrical connection layer (fig. 19; [0053]).
In regards to claim 21, the combination of Lee and Chou teaches the limitations discussed above in addressing claim 14. Lee further teaches the limitations wherein the first (48) and second (78) semiconductor dies are identical to each other (fig. 19). Zhou further teaches the limitations wherein the conductive element electrically connects (using (O) leadframe (114B)) the first and second active devices (102/120) in a series connection arrangement (fig. 1C; [0024], [0027], [0032]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lee with the aforementioned limitations taught by Zhou such that the elements of Lee are connected in series to have a compact, low-inductance chip-on-chip arrangement (Zhou Title).
In regards to claim 22, the combination of Lee and Chou teaches the limitations discussed above in addressing claim 14. Zhou further teaches the limitations wherein an upper surface of the first interconnect layer (surface of (114B) in contact with (102) on the right side of fig. 1C) and the second bottom surface of the second semiconductor die ((102) on the right side of fig. 1C) are coplanar with each other in a vertical direction (fig. 1C; [0032]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lee with the aforementioned limitations taught by Zhou such that the semiconductor dies of Lee are arranged in a coplanar manner to have a compact, low-inductance chip-on-chip arrangement (Zhou Title).
In regards to claim 23, the combination of Lee and Chou teaches the limitations discussed above in addressing claim 14. Lee further teaches the limitations wherein the first active device (e.g. transistor as implied by source/drain contacts (54/58)) comprises a first terminal (58) on the first upper surface (52) and a second terminal (54) on the first bottom surface (50), and the second active device (e.g. transistor as implied by source/drain contacts (84/88)) comprises a third terminal (84) on the second upper surface (82) and a fourth terminal (88) on the second bottom surface (80), the semiconductor device further comprising:
a first conductive material layer (54) on the first bottom surface (50), the first conductive material layer comprising the second terminal of the first active device (fig. 19; [0031-0033]); and
a second conductive material layer (88) on the second bottom surface (80), the second conductive material layer comprising the fourth terminal of the second active device (fig. 19; [0031-0033]).
In regards to claim 26, Lee teaches a method of fabricating a semiconductor device including at least first (48) and second (78) (fig. 19; Abstract) semiconductor dies, the method comprising:
providing a first semiconductor die (48) including a first active device (e.g. transistor as implied by source/drain contacts (54/58)) formed therein, the first semiconductor die comprising a first upper surface (52) and a first bottom surface (50) opposite the first upper surface (figs. 3, 19; [0031], [0050]);
electrically connecting the first semiconductor die (48) to a first leadframe (264) of the semiconductor device, the first semiconductor die being configured such that the first bottom surface (50) faces the first leadframe (264) (figs. 3, 19; [0031]);
providing a second semiconductor die (78) spaced laterally from the first semiconductor die and including a second active device (e.g. transistor as implied by source/drain contacts (84/88)) formed therein, the second semiconductor die comprising a second upper surface (82) and a second bottom surface (80) opposite the second upper surface (fig. 19);
electrically connecting the second semiconductor die to a second leadframe (270) of the semiconductor device, the second semiconductor die being configured such that the second upper surface faces the second leadframe (fig. 19; [0033], [0050]);
forming a conductive element (fig. 19: portions of (276) of leadframe (270) in contact with (48/78)) electrically connecting the first (48) and second (78) semiconductor dies (fig. 19; [0053]);
forming a first interconnect layer (portion of solder layers (65) above first die (48)) between the first upper surface (52) of the first semiconductor die and a first end of the conductive element (276), the first interconnect layer being configured to provide vertical separation (e.g. shown by stack depicted in fig. 5) and electrical connection between the first semiconductor die and the conductive element (fig. 19; [0053]); and
forming a second interconnect layer (another portion of solder layer (65) above second die (78)) between the second upper surface of the second semiconductor die and the second leadframe, the second interconnect layer being configured to provide vertical separation (e.g. shown by stack depicted in fig. 5) and electrical connection between the second semiconductor die and the second leadframe (fig. 19; [0053]).
Lee appears to be silent as to, but does not preclude, the limitations wherein the first and second dies are connected in series. Zhou teaches the limitations wherein the conductive element electrically connects (using (O) leadframe (114B)) the first and second active devices (102/120) in a series connection arrangement (fig. 1C; [0024], [0027], [0032]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Lee with the aforementioned limitations taught by Zhou such that the elements of Lee are connected in series to have a compact, low-inductance chip-on-chip arrangement (Zhou Title).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lee and Zhou as applied to claim 16 above, in view of Zhang et al. (US 2011/0233792 A1; hereinafter Zhang).
In regards to claim 18, the combination of Lee and Zhou teaches the limitations discussed above in addressing claim 16. Lee further teaches the limitations multiple electrical connection layers in different orientations (fig. 5; [0031]). The combination of Lee and Zhou appears to be silent as to, but does not preclude, the limitations further comprising: a third electrical connection layer between the first interconnect layer and a first end of the conductive element; and a fourth electrical connection layer between the second bottom surface and a second end of the conductive element laterally opposite the first end, wherein the conductive element is attached to the first and second semiconductor dies via the third and fourth electrical connection layers, respectively; however, the court in In re Harza held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced; therefore, one having ordinary skill in the art at the time the application at hand was filed would find it obvious to duplicate the electrical connection layers and their respective layouts as taught by the combination of Lee and Zhou such that the device of the combination of Lee and Zhou includes the limitations further comprising: a third electrical connection layer between the first interconnect layer and a first end of the conductive element; and a fourth electrical connection layer between the second bottom surface and a second end of the conductive element laterally opposite the first end, wherein the conductive element is attached to the first and second semiconductor dies via the third and fourth electrical connection layers, respectively. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Furthermore, Zhang teaches having additional conductive layers can improve electrical connections (Abstract).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-23 and 25-28 have been considered but are moot because the new ground of rejection does not rely the references as applied in the prior rejection of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812
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