Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
2 pending office actions • 1 art units • 2 examiners • 0 of 2 (0%) have an AI response strategy ready • 1 patents granted in the last 365 days
Ideal Semiconductor Devices Inc. has 2 pending office actions in the Semiconductors, Circuits & Optics technology area. These are assigned to 2 distinct examiners and 1 distinct art unit. TRAN, TONY is the busiest examiner, managing 1 busiest examiner pending action.
The 2 pending office actions are being reviewed by 2 distinct examiners within the same 1 distinct art unit. TRAN, TONY is responsible for 1 busiest examiner pending action. This indicates that the Semiconductors, Circuits & Optics portfolio is currently being examined by 2 distinct examiners within a single departmental group. With 2 pending office actions, the company has a focused prosecution path. The 1 distinct art unit provides a common technical framework for both cases, even though 2 distinct examiners are providing the individual reviews. TRAN, TONY handles 1 busiest examiner pending action, representing a portion of the current volume. This structure allows for technical consistency across the 2 pending office actions due to the shared 1 distinct art unit.
Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 2 (100%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| TRAN, TONY | 1 | 70.5% | +33.5% |
| CHOI, CALVIN Y | 1 | 81.8% | +17.6% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18496277 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME | CHOI, CALVIN Y | 9d |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18496277 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME | CHOI, CALVIN Y | 9d |
| 18647072 | NON-CONDUCTING EDGE TERMINATION STRUCTURES FOR A SEMICONDUCTOR DEVICE AND METHODS OF FABRICATING THE SAME | TRAN, TONY | — |
| Art Unit | Apps |
|---|---|
| 2812 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18647072 | NON-CONDUCTING EDGE TERMINATION STRUCTURES FOR A SEMICONDUCTOR DEVICE AND METHODS OF FABRICATING THE SAME | TRAN, TONY | — | §103 | Non-Final OA | — | Pending | Apr 26, 2024 |
| 18496277 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME | CHOI, CALVIN Y | 2812 | §103 | Final Rejection | 9d | Pending | Oct 27, 2023 |
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