`Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of
the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 13, 16, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kusuyama (WO 2020/100849, hereinafter Kusuyama) in view of Kawagishi et al. (US 2008/0149381, hereinafter Kawagishi).
With respect to claim 1, Kusuyama discloses a radio frequency module comprising: a mounting substrate (20 of Fig. 10A) having a first main surface (top surface) and a second main surface (bottom surface) that are opposite to each other (top and bottom surfaces of 20 are opposite to each other); a first electronic component (31) on the first main surface of the mounting substrate (Fig. 10A);
a second electronic component (32) on the second main surface of the mounting substrate; a plurality of connection terminals (50’s) on the second main surface of the mounting substrate and connected to the mounting substrate (50’s are on the second main surface of 20 and are connected to 20); and a module circuit board (91 of Fig. 10B) that faces the second main surface of the mounting substrate (91 faces the bottom surface of 20) with the second electronic component interposed between the circuit board and the second main surface (32 is interposed between 91 and the bottom surface of 20), and that is connected to the plurality of connection terminals (91 is connected to 50’s), wherein the second electronic component is located between the mounting substrate and the module circuit board (32 is between 20 and 91), wherein the module circuit board comprises: a base material that has a third main surface (top surface of 91) and a fourth main surface (bottom surface of 91), and that is connected to the plurality of connection terminals with the third main surface interposed between the base material and the plurality of connection terminals (top surface of 91 is connected to 50’s and is between the terminals and base material of 91), the third main surface and the fourth main surface being opposite to each other (top and bottom surfaces of 91), and a plurality of external connection electrodes (95’s) on the fourth main surface of the base material (95’s are on the bottom of 91), wherein the mounting substrate comprises a first conductor (bumps/connections between the lower surface of 20 and 32&50) connected to the second electronic component (Fig. 10B), wherein the base material comprises a second conductor (interconnects at the bottom surface of 91) connected to the first conductor with at least one of the plurality of connection terminals interposed between the second conductor and the first conductor (Fig. 10B), wherein at least one of the plurality of external connection electrodes is connected to the second conductor (95’s are electrically connected to the interconnects at the bottom surface of 91), and wherein the module circuit board is in contact with the second electronic component (91 is in contact with 32).
Kusuyama does not explicitly disclose that the module circuit board comprises of a wiring layer.
In an analogous art, Kawagishi discloses that the module circuit board comprises of a wiring layer (para 0029 and 0057 – circuit board comprises of wiring patterns). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Kusuyama’s method by having Kawagishi’s disclosure in order to connect different components of a semiconductor device.
With respect to claim 2, Kusuyama discloses wherein the base material is in contact with the second electronic component (Fig. 10B - 91 is in contact with 32).
With respect to claim 13, Kusuyama discloses a plurality of the second electronic components (Page 10; last para – there are multiple second electronic components), wherein the wiring layer is in contact with all of the plurality of second electronic components (91 is in contact with 32, if there are multiple 32’s than it implies that 91 is in contact with more than one second electronic components).
With respect to claim 16, Kusuyama disclose a first resin layer (Fig. 10A - top part of 41) on the first main surface of the mounting substrate that covers the first electronic component (top part of 41 covers 31); a second resin layer (bottom part of 41) between the mounting substrate and the wiring layer (Fig. 10B – bottom part of 41 is between 20 and 91); and a shield layer (60) that covers the first resin layer, an outer circumferential surface of the mounting substrate, an outer circumferential surface of the second resin layer, and an outer circumferential surface of the wiring layer (page 15; last para), wherein the shield layer is in contact with at least part of an outer circumferential surface of a ground layer of the base material of the wiring layer (page 16 – para 01).
With respect to claim 18, Kusuyama discloses wherein in the plan view in the thickness direction of the mounting substrate, a cross section of each of the plurality of connection terminals is different from a cross section of one of the plurality of external connection electrodes (Fig. 10B -cross section of 50’s and 95’s are different in thickness direction).
With respect to claim 19, Kusuyama discloses wherein the base material is thinner than the mounting substrate (Page 04- thickness of the substrate can vary).
Claims 7 and 10 - 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kusuyama/Kawagishi in view of Foster et al. (US 2011/0110064, hereinafter Foster).
With respect to claim 7, Kusuyama discloses wherein the base material is a first base material (91 of Fig. 10B), and wherein the second electronic component comprises:
a second base material that has a fifth main surface and a sixth main surface that are opposite to each other (32 comprises of top and bottom surfaces), the fifth main surface being on a mounting substrate side, the sixth main surface being on an opposite side from the mounting substrate side (Fig. 10A).
Kusuyama/Kawagish does not explicitly disclose a through hole via that penetrates through a portion between the fifth main surface and the sixth main surface.
In an analogous art, Foster discloses a through hole via that penetrates through a portion between the fifth main surface and the sixth main surface (Para 0023, 0025 and 0049 – TSV). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Kusuyama/Kawagish’s method by having Foster’s disclosure in order to interconnect different components of a semiconductor device.
With respect to claim 10, Kusuyama discloses wherein the through hole via is in contact with the wiring layer (Page 8, para 02-03).
With respect to claim 11, Kusuyama does not explicitly disclose wherein the second electronic component is a power amplifier or a low noise amplifier.
In an analogous art, Kawagishi discloses wherein the second electronic component is a power amplifier or a low noise amplifier (Para 0052 – power amplifier). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Kusuyama’s method by having Kawagishi’s disclosure in order enhance the signal strength to boost voice and data speed.
With respect to claim 12, Kusuyama does not explicitly disclose wherein the second electronic component further comprises an amplifier on the fifth main surface of the second base material.
In an analogous art, Kawagishi discloses wherein the second electronic component further comprises an amplifier on the fifth main surface of the second base material (Para 0052 – power amplifier). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Kusuyama’s method by having Kawagishi’s disclosure in order enhance the signal strength to boost voice and data speed.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over
Kusuyama/Kawagishi in view of Cheng et al. (US 2008/0151975, hereinafter Cheng).
With respect to claim 20, Kusuyama/Kawagishi discloses a communication apparatus comprising: the radio frequency module according to Claim 1.
Kusuyama/Kawagishi does not explicitly disclose a signal processing circuit configured to process a signal that passes through the radio frequency module.
In an analogous art, Cheng discloses a signal processing circuit configured to process a signal that passes through the radio frequency module (Para 0024 & 0027 - RF module to process the signal).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Kusuyama/Kawagishis’s method by having Cheng’s disclosure in order to process the signal to enable wireless communication.
Allowable Subject Matter
Claims 3-6, 8-9, 14-15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 3, none of the prior art on record disclose or render obvious the claimed limitations including “wherein in a plan view in a thickness direction of the mounting substrate, at least one of the plurality of external connection electrodes overlaps the second electronic component” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 5, none of the prior art on record disclose or render obvious the claimed limitations including “wherein in the plan view in the thickness direction of the mounting substrate, the plurality of external connection electrodes comprises an external connection electrode that overlaps one of the plurality of connection terminals” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 8, none of the prior art on record disclose or render obvious the claimed limitations including “wherein in the plan view in the thickness direction of the mounting substrate, the through hole via overlaps at least one of the plurality of external connection electrodes” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 14, none of the prior art on record disclose or render obvious the claimed limitations including “a conductor having a ground potential that is between two adjacent second electronic components of the plurality of second electronic components, wherein the conductor is in contact with the mounting substrate and the wiring layer, wherein the plurality of external connection electrodes comprises the ground electrode, and wherein in the plan view in the thickness direction of the mounting substrate, the conductor overlaps the ground electrode” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 17, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the shield layer is in contact with a surface on an opposite side of the first electronic component from a mounting substrate side, wherein the plurality of external connection electrodes comprises the ground electrode, and wherein the ground electrode is connected to a ground layer of the base material with a via conductor in the wiring layer interposed between the ground electrode and the ground layer” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Claims 4, 6, 9 and 15 have been objected because of their dependency on claims 3, 8 and 14 respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/ Primary Examiner, Art Unit 2899
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