DETAILED ACTION
This Action is responsive to the communication filed on 10/27/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Higashi (US 2022/0115246), in view of Otsuka (US 2023/0411338).
Regarding claim 1, Higashi (see, e.g., FIG. 3, FIG. 4) discloses a semiconductor device, comprising:
a first semiconductor chip 22 having a first output electrode e.g., control electrode of 22 on a front surface e.g., top of 22 thereof and a first input electrode e.g., input electrode of 22 on a rear surface e.g., bottom of 22 thereof (Para 0034);
a first lead frame 46 including a first chip region 46a to which the first input electrode e.g., bottom of 22 of the first semiconductor chip 22 is bonded, and a first wiring region 46c (Para 0028, Para 0031, Para 0037);
a second semiconductor chip 21 having a second output electrode e.g., control electrode of 21 on a front surface e.g., top of 21 thereof and a second input electrode e.g., input electrode of 21 on a rear surface e.g., bottom of 21 thereof, the second semiconductor chip 21 being adjacent to the first chip region 46a (Para 0034);
an other lead frame 45 electrically connected to the second output electrode e.g., control electrode of 21 of the second semiconductor chip 21 (Para 0037); and
a wiring member 22e connected to the second output electrode e.g., control electrode of 21 of the second semiconductor chip 21 and to the first wiring region 46c of the first lead frame 46,
Although the semiconductor device as disclosed by Higashi shows substantial features of the claimed invention, Higashi fails to expressly teach wiring member connected to the second output electrode of the second semiconductor chip and to the first wiring region of the first lead frame via an insulating member.
Otsuka (see, e.g., FIG. 10) teaches a wiring member 42 connected to the second semiconductor chip 10B and to the first wiring region 22A of 20 (22A, 22B) of the first lead frame 20 (22A, 22B) via an insulating member 29 for the purpose of stabilizing the shape of the input terminal (Para 0050, Para 0051, Para 0060).
The combination of Higashi (see, e.g., FIG. 3, FIG. 4) / Otsuka (see, e.g., FIG. 10) teaches wiring member 42 (as taught by Otsuka) connected to the second output electrode e.g., control electrode of 21 (as taught by Higashi) of the second semiconductor chip 21 (as taught by Higashi) and to the first wiring region 46c (as taught by Higashi) of the first lead frame 46 (as taught by Higashi) via an insulating member 29 (as taught by Otsuka).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wiring member of Higashi include the wiring member and insulating member as described by Otsuka for the purpose of stabilizing the shape of the input terminal (Para 0050, Para 0051, Para 0060).
Regarding claim 2, Higashi (see, e.g., FIG. 3, FIG. 4) teaches the semiconductor device according to claim 1, further comprising: a second lead frame 47, wherein the second lead frame 47 includes a second chip region 47a adjacent to the first chip region 46a, and a second wiring region 43 to which the first output electrode e.g., control electrode of 22 of the first semiconductor chip 22 is electrically connected, the second input electrode e.g., input electrode of 21 of the second semiconductor chip 21 being bonded to the second chip region 47a (Para 0031, Para 0034, Para 0037).
Regarding claim 3, Higashi (see, e.g., FIG. 3, FIG. 4) teaches the semiconductor device according to claim 2, wherein the second chip region 47a of the second lead frame 47 is adjacent to and faces the first chip region 46a in a first direction e.g., x-direction, and the first wiring region 46c of the first lead frame 46 extends in the first direction e.g., x-direction at a first side e.g., bottom side of the second chip region 47a of the second lead frame 47.
Regarding claim 14, the combination of Higashi (see, e.g., FIG. 3, FIG. 4) / Otsuka (see, e.g., FIG. 10) teaches the semiconductor device according to claim 1, wherein a portion of the wiring member 42 (as taught by Otsuka) overlapping the first wiring region 46c (as taught by Higashi) of the first lead frame 46 (as taught by Higashi) extends along the first wiring region 46c (as taught by Higashi) in a plan view of the semiconductor device e.g., device of Higashi FIG. 3 (as taught by Higashi).
Regarding claim 15, the combination of Higashi (see, e.g., FIG. 3, FIG. 4) / Otsuka (see, e.g., FIG. 10) teaches the semiconductor device according to claim 1, wherein the wiring member 42 (as taught by Otsuka) is connected to the second output electrode e.g., control electrode of 21 (as taught by Higashi) via a conductive spacer 33 (as taught by Otsuka) (Higashi: Para 0034; Otsuka: Para 0066).
Regarding claim 16, the combination of Higashi (see, e.g., FIG. 3, FIG. 4) / Otsuka (see, e.g., FIG. 10) teaches the semiconductor device according to claim 1, wherein the wiring member 42 (as taught by Otsuka) has a portion 421c (as taught by Otsuka) projecting toward the second output electrode e.g., control electrode of 21 (as taught by Higashi) so that the wiring member 42 (as taught by Otsuka) is connected at the projecting portion 421c (as taught by Otsuka) to the second output electrode e.g., control electrode of 21 (as taught by Higashi).
Regarding claim 17, Otsuka (see, e.g., FIG. 10) teaches the semiconductor device according to claim 1, wherein the insulating member 29 is a dielectric (Para 0060).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Higashi (US 2022/0115246), in view of Otsuka (US 2023/0411338), and further in view of Michiaki (US 2021/0359592).
Regarding claim 18, although the semiconductor device as disclosed by Higashi/Otsuka shows substantial features of the claimed invention, Higashi/Otsuka fails to expressly teach the semiconductor device according to claim 1, wherein the insulating member is a chip capacitor.
Michiaki (see, e.g., FIG. 1) teaches the insulating member 11, e.g., stack ceramic capacitor is a chip capacitor for the purpose of providing a snubber circuit within the semiconductor device that sufficiently reduces noise in high-speed switching operations (Para 0017, Para 0032, Para 0035, Para 0038, Para 0042, Para 0049).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the insulating member of Higashi/Otsuka to the insulating member being a chip capacitor e.g., stack ceramic capacitor as described by Michiaki for the purpose of providing a snubber circuit within the semiconductor device that sufficiently reduces noise in high-speed switching operations (Para 0017, Para 0042, Para 0049).
Allowable Subject Matter
Claims 4-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Prosecution Insights