DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 22-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/02/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 7-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Braunisch et al. (U.S. Publication No. 2008/0150125 A1; hereinafter Braunisch)
With respect to claim 1, Braunisch discloses a semiconductor device assembly, comprising: a substrate [104] having a bore [120] that extends through the substrate; a semiconductor die [102,108] disposed on the substrate; and a thermally-conductive channel [114] extending through the bore, the thermally-conductive channel having a first end located at a same side of the substrate as the semiconductor die, and a second end located at an opposite side of the substrate from the semiconductor die (See Figure 2).
With respect to claim 2, Braunisch discloses wherein the thermally-conductive channel comprises copper (see ¶[0017]).
With respect to claim 3, Braunisch discloses wherein the semiconductor device assembly is in a board-on-chip configuration (see Figure 2).
With respect to claim 4, Braunisch discloses wherein the first end of the thermally-conductive channel contacts the semiconductor die (See Figure 2).
With respect to claim 7, Braunisch discloses wherein the thermally-conductive channel includes a narrower portion and a wider portion (See Figure 5C).
With respect to claim 8, Braunisch discloses wherein the thermally-conductive channel is aligned with an area of the semiconductor die that is associated with a higher operating temperature than an operating temperature of another area of the semiconductor die (see ¶[0033]).
With respect to claim 9, Braunisch discloses an additional thermally-conductive channel extending through the bore (see Figure 2).
With respect to claim 10, Braunisch discloses a casing [118] surrounding the semiconductor die (see Figure 6; casing also constructed utilizing [106] and [102]).
With respect to claim 11, Braunisch discloses a die attach film between the semiconductor die and the substrate (see Figure 2; die is connected via [106] which rests on die attach film).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Braunisch in view of Lee et al. (U.S. Patent No. 9,196,575 B1; hereinafter Lee)
With respect to claim 12, Braunisch discloses an apparatus, comprising: and a semiconductor device assembly, comprising: a substrate [104] having a bore [120] that extends through the substrate, a semiconductor die [102,108] disposed on the substrate; and a thermally-conductive channel [114], extending through the bore, between the semiconductor die and the circuit board (See Figure 2).
Braunisch fails to disclose a circuit board; wherein the substrate is electrically connected to the circuit board, wherein the thermally-conductive channel is configured to transfer heat from the semiconductor die to the circuit board. In the same field of endeavor, Lee teaches a circuit board [305]; wherein the substrate [102] is electrically connected to the circuit board, wherein the thermally-conductive channel [401] is configured to transfer heat from the semiconductor die to the circuit board (see Lee Figure 2A; Column 3, lines 30-35). Implementation of a circuit board as taught by Lee allows for connection of the device of Braunisch to exterior devices and heat dissipation from semiconductor die structures within the device (see Lee Column 3, lines 30-35). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 13, the combination of Braunisch and Lee discloses wherein the semiconductor device assembly is in a board-on-chip configuration (see Braunisch Figure 2).
With respect to claim 14, the combination of Braunisch and Lee discloses wherein the substrate is electrically connected to the circuit board via a ball grid array [103] (see Lee Figure 2A).
With respect to claim 15, the combination of Braunisch and Lee discloses wherein the thermally-conductive channel contacts the semiconductor die (See Braunisch Figure 2).
With respect to claim 16, the combination of Braunisch and Lee discloses a thermal interface material disposed on the circuit board, wherein the thermally-conductive channel contacts the thermal interface material (see Lee Column 4, lines 9-15).
With respect to claim 17, the combination of Braunisch and Lee discloses wherein the thermally-conductive channel includes a narrower portion and a wider portion, and wherein the wider portion has a thermal connection to the circuit board (See Braunisch Figure 5C and Lee Figure 2A). With respect to claim 18, the combination of Braunisch and Lee discloses wherein the thermally-conductive channel has a thermal connection to a via [316] in the circuit board (see Lee Figure 2A).
With respect to claim 19, the combination of Braunisch and Lee discloses an additional thermally-conductive channel, extending through the bore, between the semiconductor die and the circuit board, wherein the additional thermally-conductive channel is configured to transfer heat from the semiconductor die to the circuit board (see Braunisch Figure 2 and Lee Figure 2A).
With respect to claim 20, the combination of Braunisch and Lee discloses wherein a thermal connection of the thermally-conductive channel to the circuit board is at a gap between a first row of electrical contacts of the circuit board and a second row of electrical contacts of the circuit board (see Lee Figure 2A)
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Braunisch in view of Khan et al. (U.S. Publication No. 2006/0065972 A1; hereinafter Khan).
With respect to claim 5, Braunisch fails to disclose an encapsulant extending through the bore, wherein the thermally-conductive channel extends through the encapsulant but does disclose isolating sidewalls [124] (see Figure 5C). In the same field of endeavor, Khan teaches an encapsulant [310] extending through the bore, wherein the thermally-conductive channel [320] extends through the encapsulant (see Figure 3). Implementation of an encapsulant surrounding the thermally-conductive channel as taught by Khan allows for physical and conductive isolation from surrounding device layers (see Figure 3). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 6, the combination of Braunisch and Khan discloses a wire bond [308] from a bottom of the semiconductor die [302] to a bottom of the substrate [314], wherein the encapsulant encapsulates the wire bond (See Khan Figure 3).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Braunisch in view of Lee as applied to claim 12 above, and further in view of Khan.
With respect to claim 21, the combination of Braunisch and Lee fails to disclose an encapsulant extending through the bore, wherein the thermally-conductive channel extends through the encapsulant.
In the same field of endeavor, Khan teaches an encapsulant [310] extending through the bore, wherein the thermally-conductive channel [320] extends through the encapsulant (see Figure 3). Implementation of an encapsulant surrounding the thermally-conductive channel as taught by Khan allows for physical and conductive isolation from surrounding device layers (see Figure 3). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Refai-Ahmed et al. (U.S. Publication No. 2012/0075807 A1) discloses a semiconductor chip with thermal conductors
Yoshida (U.S. Patent No. 11,776,903 B2) discloses a semiconductor package with thermal conductor
Jafari et al. (U.S. Publication No. 2010/0103604 A1) discloses a semiconductor package with thermal conductors
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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