DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I in the reply filed on 02/23/2026 is acknowledged. The traversal is on the ground(s) that both sets of claims are aligned because the claim element “laser direct structuring (LDS) material” has the same definition in both sets of claims, citing “molding” vs “molded” in claims 1 and 9 respectively. This is not found persuasive because “molded” constitutes a product-by-process claim limitations. It has been held that "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)). Therefore another and materially different process can produce the device of Invention II and would likely raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph, and acquire a separate status in the art in view of different classification than that of Invention I.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 4-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tiziani et al. (U.S. Publication No. 2021/0305191 A1; hereinafter Tiziani). With respect to claim 1, Tiziani discloses a method, comprising: arranging at least one semiconductor die [12] on a die pad [10b] in a leadframe, the leadframe comprising an array of electrically conductive leads around the die pad (see ¶[0038]); molding laser direct structuring (LDS) material [16] onto the at least one semiconductor die arranged on the die pad, the LDS material having a front surface opposite the leadframe; electrically coupling the at least one semiconductor die arranged on the die pad with selected ones of the electrically conductive leads in the array via electrical connections, wherein the electrical connections comprise: electrically conductive formations exposed at the front surface of the LDS material (see Figure 2E); electrically conductive vias [20b] between the at least one semiconductor die arranged on the die pad and the front surface of the LDS material; and electrically conductive lines [20a] over the front surface of the LDS material, the electrically conductive lines coupling selected ones of the electrically conductive formations with selected ones of the electrically conductive vias (see Figure 2H), wherein the providing the electrically conductive vias and the electrically conductive lines comprises applying laser beam energy to the front surface of the laser direct structuring material at spatial positions located as a function of the electrically conductive formations exposed at the front surface of the LDS material (see ¶[0071-0075]).
With respect to claim 4, Tiziani discloses wherein the electrically conductive formations exposed at the front surface of the LDS material comprise electrically conductive leads in the array, wherein the die pad is downset with respect to the electrically conductive leads in the array (See Figure 2B).
With respect to claim 5, Tiziani discloses growing electrically conductive material at the spatial positions located as a function of the electrically conductive formations exposed at the front surface of the LDS material to which laser beam energy has been applied (See ¶[0074]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tiziani in view of Chiang et al. (U.S. Publication No. 2023/0170226 A1; hereinafter Chiang)
With respect to claim 2, Tiziani fails to disclose wherein the electrically conductive formations exposed at the front surface of the LDS material comprise pillar-like extensions of the electrically conductive leads in the array, with the LDS material molded onto the at least one semiconductor die arranged on the die pad leaving uncovered the distal ends of the pillar-like extensions. In the same field of endeavor, Chiang teaches wherein the electrically conductive formations exposed at the front surface of the LDS material comprise pillar-like extensions [104] of the electrically conductive leads in the array (see Figure 1H), with the LDS material molded onto the at least one semiconductor die arranged on the die pad leaving uncovered the distal ends of the pillar-like extensions (See Figure 1H and ¶[0055]). Implementation of pillar-like extensions as taught by Chiang allows for improved I/O connections allowing for the entirety of the pillar to be accessible for connectivity (See ¶[0061]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention. With respect to claim 7, the combination of Tiziani and Chaing discloses wherein the pillar-like extensions of the electrically conductive leads in the array have a first height that is equal to a first depth of the LDS material molded onto at least one semiconductor die (see Chiang Figure 1H).
Claim(s) 3, 6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tiziani in view of Graziosi et al. (U.S. Publication No. 2021/0305203 A1; hereinafter Graziosi)
With respect to claim 3, Tiziani discloses wherein the molded LDS material exhibits cavities in the front surface of the LDS material extending towards electrically conductive leads in the array (see Figure 2E), and growing electrically conductive material in the cavities, wherein the electrically conductive material grown in the cavities provides electrically conductive formations grown on electrically conductive leads in the array, the electrically conductive formations exposed at the front surface of the LDS material (see ¶[0078]), but fails to disclose molding LDS material onto the at least one semiconductor die arranged on the die pad using a mold provided with punches protruding towards electrically conductive leads in the array In the same field of endeavor, Graziosi teaches using a mold provided with punches protruding towards electrically conductive leads in the array (see ¶[0073-0076]). Implementation of a punch system allows for tool flexibility that allows for adding and removing punches and position changes to allow for electrical connections where desired (see Graziosi ¶[0074]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 6, the combination of Tiziani and Graziosi discloses wherein the growing electrically conductive material comprises plating metal material, preferably copper (see Tiziani ¶[0085]).
With respect to claim 8, the combination of Tiziani and Graziosi discloses wherein the punches form in the molded LDS material the cavities in the front surface of the LDS material extending towards electrically conductive leads in the array (see Tiziani Figure 2E).
Claim(s) 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tiziani in view of Do et al. (U.S. Publication No. 2013/0154105 A1; hereinafter Do)
With respect to claim 13, Tiziani discloses a method, comprising: forming a die [12] on a recessed portion of a die pad [10b] in a leadframe, the leadframe comprising a plurality of electrically conductive leads surrounding the die pad; forming a laser direct structuring (LDS) molding compound [16], the LDS molding compound having a first surface coupled to the leadframe and a second surface opposite the first surface; and forming a conductive layer [20a/b] in the plurality of cavities and on the second surface of the LDS molding compound (see Figure 2H ¶[0071-0075]).
Tiziani fails to explicitly disclose forming a mold chase on the leadframe, the mold chase including a plurality of punches that are coupled directly to the electrically conductive leads; removing the mold chase to expose a plurality of cavities extending from the second surface of the LDS molding compound to the electrically conductive leads. In the same field of endeavor, Do teaches creating openings coupled directly to the electrically conductive leads; removing the mold chase to expose a plurality of cavities extending from the second surface of the LDS molding compound to the electrically conductive leads (See ¶[0102]). Implementation of a mold chase with integrated punches to create cavities for coupling electrically conductive leads as taught by Do allows for easily repeatable formation of a molding compound to protect the die structure while exposing surfaces for electrical connection (See Tiziani ¶[0102]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 14, the combination of Tiziani and Do discloses before the forming a conductive layer, forming a plurality of vias from the second surface of the LDS molding compound to the die (see Tiziani Figure 2E)
With respect to claim 15, the combination of Tiziani and Do discloses wherein the plurality of vias are formed using a laser drilling through the LDS molding compound (see Tiziani ¶[0051-0055]).
With respect to claim 16, the combination of Tiziani and Do discloses wherein the die includes a plurality of bonding pads and each of the plurality of vias extends from the second surface of the LDS molding compound to one of the plurality of bonding pads on the die (See Tiziani Figure 2E).
With respect to claim 17, the combination of Tiziani and Do discloses forming, with a laser, a plurality of traces on the second surface of the LDS molding compound, the traces extending from one of the plurality of vias to an adjacent one of the trenches (See Tiziani Figure 2G and ¶[0058]).
With respect to claim 18, the combination of Tiziani and Do discloses wherein the conductive layer is formed in the plurality of vias and in the plurality of traces, the conductive layer coupling each trench to an adjacent one of the plurality of vias along one of the plurality of traces (See Tiziani Figure 2G and ¶[0058]).
With respect to claim 19, the combination of Tiziani and Do discloses wherein the forming a conductive layer in the plurality of cavities and on the second surface of the LDS molding compound includes depositing metal into the plurality of cavities and on the second surface of the LDS molding compound (See Tiziani Figure 2G).
With respect to claim 20, the combination of Tiziani and Do discloses comprising forming an insulating layer [24] on the second surface of the LDS molding compound (see Tiziani Figure 2H).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. - Derai et al. (U.S. Publication No. 2019/0115287 A1) discloses leadframe with LDS connected die
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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