DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-13, 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harazono et al. (US 2011/0314666 A1 hereinafter referred to as “Harazono”).
With respect to claim 1, Harazono discloses, in Figs.1A-7, a semiconductor device, comprising: a first circuit (2) comprising a silicon material, the first circuit being characterized by a first coefficient of thermal expansion (see Par.[0035] wherein the electronic component 2 is a semiconductor element such as an IC or an LSI, where the base material is made from a semiconductor material such as silicon, germanium, gallium arsenide, gallium arsenide phosphide, gallium nitride, or silicon carbide; such an electronic component 2 has the coefficient of thermal expansion in each direction set to greater than or equal to 3 ppm/.degree. C. and smaller than or equal to 5 ppm/.degree. C); a substrate (4) coupled to the first circuit (2), the substrate (4) being characterized by a second coefficient of thermal expansion, the substrate (4) comprising: a first layer (10a) coupled to the first circuit (2) (see Par.[0049] wherein the first resin layer 10a has the thickness set to greater than or equal to 2 .mu.m and smaller than or equal to 20 .mu.m, the coefficient of thermal expansion of the first resin layer 10a in the planar direction set to greater than or equal to 0 ppm/.degree. C. and smaller than or equal to 30 ppm/.degree. C., the coefficient of thermal expansion of the first resin layer 10a in the thickness direction set to greater than or equal to 20 ppm/.degree. C. and smaller than or equal to 50 ppm/.degree. C., and the Young's modulus of the first resin layer 10a set to greater than or equal to 2.5 GPa and smaller than or equal to 10 GPa; the first resin layer 10a, polyimide resin is used); a second layer (10b) coupled to the first layer (10a), the second layer (10b) comprising a first wiring (11-13) (see Par.[0053]-[0054] wherein the second resin layer 10b has the thickness set to greater than or equal to 2 .mu.m and smaller than or equal to 20 .mu.m, the coefficient of thermal expansion of the second resin layer 10b in each direction set to greater than or equal to 10 ppm/.degree. C. and smaller than or equal to 100 ppm/.degree. C., the coefficient of thermal expansion of the second resin layer 10b in the planar direction set to greater than or equal to two times and smaller than or equal to 100 times the first resin layer 10a, the Young's modulus of the second resin layer 10b set to greater than or equal to 0.05 GPa and smaller than or equal to 0.5 GPa, and the Young's modulus thereof set to greater than or equal to 0.0005 times and smaller than or equal to 0.2 times the first resin layer 10a; the second resin layer 10b may be epoxy resin, bismaleimide triazine resin, cyanate resin, amide resin, or the like; see Par.[0047] wherein a plurality of conductive layers 11, a metal layer 12, and a via conductor 13); a third layer (7) coupled to the second layer (10b), the third layer comprising a first via (8-9), the third layer (7) being characterized by a third coefficient of thermal expansion, the third coefficient of thermal expansion being associated with the second coefficient of thermal expansion (see Par.[0040]-[0042] wherein the base body 7 has the thickness set to greater than or equal to 0.1 mm and smaller than or equal to 1 mm, the coefficient of thermal expansion of the base body 7 in the planar direction set to greater than or equal to 5 ppm/.degree. C. and smaller than or equal to 30 ppm/.degree. C., the coefficient of thermal expansion of the base body 7 in the thickness direction set to greater than or equal to 15 ppm/.degree. C. and smaller than or equal to 50 ppm/.degree. C., and the Young's modulus of the base body 7 set to greater than or equal to 5 GPa and smaller than or equal to 30 GPa; the resin material contained in the base body 7, a resin material such as epoxy resin, bismaleimide triazine resin, cyanate resin, poly(p-phenylenebenzobisoxazole, wholly aromatic polyamide resin, polyimide resin, aromatic liquid crystal polyester resin, polyether ether ketone resin or polyether ketone resin may be used; see Par.[0065] wherein the resin material, or the like is then filled inside the through-hole conductor 8 to form the insulator 9); and a fourth layer/(lower circuit layer 6 or 10b) coupled to the third layer (7), the fourth layer comprising a second wiring (11-13); wherein a ratio of the first coefficient of thermal expansion (e.g.; 30 ppm/.degree. C.) to the second coefficient (e.g.; 50 ppm/.degree. C.) of thermal expansion is greater than or equal to 3:5 (see Par.[0047] wherein the pair of circuit layers 6 are formed above and below the core substrate 5, as described above; as shown in FIGS. 1A and 1B, the circuit layer 6 includes a plurality of insulating layers 10, a plurality of conductive layers 11, a metal layer 12, and a via conductor 13).
With respect to claim 2, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein the first layer (10a) comprises a passivation material (see Par.[0049] wherein the first resin layer 10a has the thickness set to greater than or equal to 2 .mu.m and smaller than or equal to 20 .mu.m, the coefficient of thermal expansion of the first resin layer 10a in the planar direction set to greater than or equal to 0 ppm/.degree. C. and smaller than or equal to 30 ppm/.degree. C., the coefficient of thermal expansion of the first resin layer 10a in the thickness direction set to greater than or equal to 20 ppm/.degree. C. and smaller than or equal to 50 ppm/.degree. C., and the Young's modulus of the first resin layer 10a set to greater than or equal to 2.5 GPa and smaller than or equal to 10 GPa; the first resin layer 10a, polyimide resin is used).
With respect to claim 3, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein: the second layer (10b) comprises a first dielectric material, and the first dielectric material comprises an organic material; and the fourth layer (6) comprises a second dielectric material, the second dielectric material comprises an inorganic material (see Par.[0047] wherein the circuit layer 6 includes a plurality of insulating layers 10).
With respect to claim 4, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein the first wiring (11,13) is coupled to the third layer (7) and the second wiring (11, 13) is coupled to the third layer (7).
With respect to claim 5, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein the first circuit (11-13) is coupled to the first layer (10a) via a first joint (3), the first layer (10a) comprises a first connection (11), and the first connection (11) is coupled to the first joint (3) (see Par.[0034] wherein the mounting structure 1 includes an electronic component 2 and a circuit board 4 on which the electronic component 2 is flip chip mounted through a bump 3; see Par.[0047]-[0048] wherein the plurality of the conductive layers 11 are arranged on the base body 7 and the insulating layer 10 and are apart from each other in a thickness direction, and the conductive layers 11 on the insulating layer 10 are apart from each other in a planar direction).
With respect to claim 6, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein the first circuit (2) comprises a memory, a thermal component, a mechanical component, an optical component, or an electrical component (see Par.[0034]-[0036] wherein the electronic component 2 is a semiconductor element such as an IC or an LSI, where the base material is made from a semiconductor material such as silicon, germanium, gallium arsenide, gallium arsenide phosphide, gallium nitride, or silicon carbide; such an electronic component 2 has the coefficient of thermal expansion in each direction set to greater than or equal to 3 ppm/.degree. C. and smaller than or equal to 5 ppm/.degree. C).
With respect to claim 7, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein the third layer comprises a glass material, a ceramic material, a diamond material, or a silicon material (see Par.[0043] wherein the glass fiber, resin fiber, carbon fiber, metal fiber, or the like may be used as the fiber).
With respect to claim 8, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein: the first wiring comprises a second via, the second via comprises a metal material (11-13); and the second wiring comprises a third via, the third via comprises a metal material (11-13) (see Par.[0047]-[0048] wherein a plurality of conductive layers 11, a metal layer 12, and a via conductor 13; see Par.[0061] wherein a metal material such as titanium, molybdenum, chrome, or nickel chrome alloy may be used to form the via conductor 13).
With respect to claim 9, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein the second coefficient of thermal expansion is less than 10 ppm/°C (see Par.[0053]-[0054] wherein the second resin layer 10b has the thickness set to greater than or equal to 2 .mu.m and smaller than or equal to 20 .mu.m, the coefficient of thermal expansion of the second resin layer 10b in each direction set to greater than or equal to 10 ppm/.degree. C. and smaller than or equal to 100 ppm/.degree. C., the coefficient of thermal expansion of the second resin layer 10b in the planar direction set to greater than or equal to two times and smaller than or equal to 100 times the first resin layer 10a, the Young's modulus of the second resin layer 10b set to greater than or equal to 0.05 GPa and smaller than or equal to 0.5 GPa, and the Young's modulus thereof set to greater than or equal to 0.0005 times and smaller than or equal to 0.2 times the first resin layer 10a; the second resin layer 10b may be epoxy resin, bismaleimide triazine resin, cyanate resin, amide resin, or the like).
With respect to claim 10, Harazono discloses, in Figs.1A-7, a semiconductor device, comprising: a first circuit (2), the first circuit (2) being characterized by a first coefficient of thermal expansion (see Par.[0035] wherein the electronic component 2 is a semiconductor element such as an IC or an LSI, where the base material is made from a semiconductor material such as silicon, germanium, gallium arsenide, gallium arsenide phosphide, gallium nitride, or silicon carbide; such an electronic component 2 has the coefficient of thermal expansion in each direction set to greater than or equal to 3 ppm/.degree. C. and smaller than or equal to 5 ppm/.degree. C); a substrate (4) coupled to the first circuit (2), the substrate (4) being characterized by a first thickness and a second coefficient of thermal expansion, the substrate comprising: a first layer (10a) coupled to the first circuit (2) (see Par.[0049] wherein the first resin layer 10a has the thickness set to greater than or equal to 2 .mu.m and smaller than or equal to 20 .mu.m, the coefficient of thermal expansion of the first resin layer 10a in the planar direction set to greater than or equal to 0 ppm/.degree. C. and smaller than or equal to 30 ppm/.degree. C., the coefficient of thermal expansion of the first resin layer 10a in the thickness direction set to greater than or equal to 20 ppm/.degree. C. and smaller than or equal to 50 ppm/.degree. C., and the Young's modulus of the first resin layer 10a set to greater than or equal to 2.5 GPa and smaller than or equal to 10 GPa; the first resin layer 10a, polyimide resin is used); a second layer (10b) coupled to the first layer (10a), the second layer (10b) comprising a first wiring (11-13), and the second layer (10b) being characterized by a second thickness (see Par.[0053]-[0054] wherein the second resin layer 10b has the thickness set to greater than or equal to 2 .mu.m and smaller than or equal to 20 .mu.m, the coefficient of thermal expansion of the second resin layer 10b in each direction set to greater than or equal to 10 ppm/.degree. C. and smaller than or equal to 100 ppm/.degree. C., the coefficient of thermal expansion of the second resin layer 10b in the planar direction set to greater than or equal to two times and smaller than or equal to 100 times the first resin layer 10a, the Young's modulus of the second resin layer 10b set to greater than or equal to 0.05 GPa and smaller than or equal to 0.5 GPa, and the Young's modulus thereof set to greater than or equal to 0.0005 times and smaller than or equal to 0.2 times the first resin layer 10a; the second resin layer 10b may be epoxy resin, bismaleimide triazine resin, cyanate resin, amide resin, or the like; see Par.[0047] wherein a plurality of conductive layers 11, a metal layer 12, and a via conductor 13); a third layer (7) coupled to the second layer (10b), the third layer (7) comprising a first via (8-9), the third layer (7) being characterized by a third thickness/( the thickness set to greater than or equal to 0.1 mm and smaller than or equal to 1 mm), and the third thickness being greater than the second thickness/(the thickness set to greater than or equal to 2 .mu.m and smaller than or equal to 20 .mu.m) (see Par.[0040]-[0042] wherein the base body 7 has the thickness set to greater than or equal to 0.1 mm and smaller than or equal to 1 mm, the coefficient of thermal expansion of the base body 7 in the planar direction set to greater than or equal to 5 ppm/.degree. C. and smaller than or equal to 30 ppm/.degree. C., the coefficient of thermal expansion of the base body 7 in the thickness direction set to greater than or equal to 15 ppm/.degree. C. and smaller than or equal to 50 ppm/.degree. C., and the Young's modulus of the base body 7 set to greater than or equal to 5 GPa and smaller than or equal to 30 GPa; the resin material contained in the base body 7, a resin material such as epoxy resin, bismaleimide triazine resin, cyanate resin, poly(p-phenylenebenzobisoxazole, wholly aromatic polyamide resin, polyimide resin, aromatic liquid crystal polyester resin, polyether ether ketone resin or polyether ketone resin may be used; see Par.[0065] wherein the resin material, or the like is then filled inside the through-hole conductor 8 to form the insulator 9); and a fourth layer (10b) coupled to the third layer (7), the fourth layer (6) comprising a second wiring (11-13), the fourth layer being characterized by a fourth thickness, the third thickness being greater than the fourth thickness; wherein the third thickness/( the thickness set to greater than or equal to 0.1 mm and smaller than or equal to 1 mm) is greater than 60% of the first thickness/(the thickness set to greater than or equal to 2 .mu.m and smaller than or equal to 20 .mu.m).
With respect to claim 11, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein the first circuit (2) comprises a memory, a thermal component, a mechanical component, an optical component, or an electrical component (see Par.[0034]-[0036] wherein the electronic component 2 is a semiconductor element such as an IC or an LSI, where the base material is made from a semiconductor material such as silicon, germanium, gallium arsenide, gallium arsenide phosphide, gallium nitride, or silicon carbide; such an electronic component 2 has the coefficient of thermal expansion in each direction set to greater than or equal to 3 ppm/.degree. C. and smaller than or equal to 5 ppm/.degree. C).
With respect to claim 12, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein the third layer comprises a glass material, a ceramic material, a diamond material, or a silicon material (see Par.[0043] wherein the glass fiber, resin fiber, carbon fiber, metal fiber, or the like may be used as the fiber).
With respect to claim 13, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein a ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is greater than or equal to 3:5 (see Par.[0035] wherein the electronic component 2 is a semiconductor element such as an IC or an LSI, where the base material is made from a semiconductor material such as silicon, germanium, gallium arsenide, gallium arsenide phosphide, gallium nitride, or silicon carbide; such an electronic component 2 has the coefficient of thermal expansion in each direction set to greater than or equal to 3 ppm/.degree. C. and smaller than or equal to 5 ppm/.degree. C; see Par.[0049] wherein the first resin layer 10a has the thickness set to greater than or equal to 2 .mu.m and smaller than or equal to 20 .mu.m, the coefficient of thermal expansion of the first resin layer 10a in the planar direction set to greater than or equal to 0 ppm/.degree. C. and smaller than or equal to 30 ppm/.degree. C., the coefficient of thermal expansion of the first resin layer 10a in the thickness direction set to greater than or equal to 20 ppm/.degree. C. and smaller than or equal to 50 ppm/.degree. C., and the Young's modulus of the first resin layer 10a set to greater than or equal to 2.5 GPa and smaller than or equal to 10 GPa; the first resin layer 10a, polyimide resin is used).
With respect to claim 15, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein the second coefficient of thermal expansion is less than 10 ppm/°C.
With respect to claim 16, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein the first wiring is coupled to the third layer.
With respect to claim 17, Harazono discloses, in Figs.1A-7, the semiconductor device, wherein the second thickness is less than or equal to 30 um, and the fourth thickness is less than or equal to 30 um.
Claims 1, 11-12, 14, 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pietambaram et al. (US 2022/0189880 A1 hereinafter referred to as “Pietambaram”).
With respect to claim 10, Pietambaram discloses, in Figs.1-22, a semiconductor device, comprising: a first circuit (102), the first circuit being characterized by a first coefficient of thermal expansion (see Par.[0017] wherein an example microelectronic assembly 100 including multiple dies 102); a substrate (110) coupled to the first circuit (102), the substrate being characterized by a first thickness and a second coefficient of thermal expansion, the substrate comprising: a first layer (121) coupled to the first circuit (102); a second layer (106) coupled to the first layer (121), the second layer (106) comprising a first wiring (122), and the second layer (106) being characterized by a second thickness (see Par.[0019] wherein the microelectronic structure 110 may include a surface insulation material 106 at its top and bottom faces, around the proximate conductive contacts 120/121; the thickness of the metal lines of the conductive contacts 120/121 may be between 5 microns and 25 microns; the surface insulation material 106 may include a solder resist and/or other dielectric materials that may provide surface electrical insulation and may be compatible with solder-based or non-solder-based interconnects, as appropriate; see Par.[0024] wherein an underfill material 142 may be disposed between the dies 102 and the microelectronic structure 110); a third layer (112-1) coupled to the second layer (106), the third layer (112-2) comprising a first via (116), the third layer being characterized by a third thickness, and the third thickness being greater than the second thickness; and a fourth layer (106) coupled to the third layer (112, 114), the fourth layer (106) comprising a second wiring, the fourth layer being characterized by a fourth thickness, the third thickness being greater than the fourth thickness; wherein the third thickness/(thickness of 112)/(e.g., between 100 microns and 200 microns) is greater than 60% of the first thickness/(thickness of 121)/(e.g., between 25 microns and 70 microns, between 25 microns and 65 microns, between 40 microns and 70 microns, less than 36 microns, or less than 25 microns) (see Par.[0021] wherein the thickness of the glass core 114 may be between 350 microns and 500 microns; the conductive contacts 121 (which may be equal to the pitch of the conductive contacts 138-1 of the bridge component 104) may be less than 70 microns (e.g., between 25 microns and 70 microns, between 25 microns and 65 microns, between 40 microns and 70 microns, less than 36 microns, or less than 25 microns); in some embodiments, the pitch of the TGVs 118 may be between 75 microns and 200 microns (e.g., between 75 microns and 150 microns); the diameters of the TGVs 118 may be between 35 microns and 100 microns (e.g., between 35 microns and 75 microns); a thickness of a metallization region 112 of a microelectronic structure 110 may be between 30 microns and 200 microns (e.g., between 100 microns and 200 microns); a thickness of the microelectronic structure 110 may be between 600 microns and 1000 microns; a thickness of a metallization region 112 of a microelectronic structure 110 may be between 30 microns and 200 microns (e.g., between 100 microns and 200 microns). In some embodiments, a thickness of the microelectronic structure 110 may be between 600 microns and 1000 microns; see Par.[0159]-[0162] wherein in Examples 65-75, and further specifies that a thickness of the metallization region is between 30 microns and 200 microns; see Par.[0024] wherein backside metallization 146 may be present on the “top” faces of the dies 102, as shown in FIG. 1).
With respect to claim 11, Pietambaram discloses, in Figs.1-22, the semiconductor device, wherein the first circuit (102) comprises a memory, a thermal component, a mechanical component, an optical component, or an electrical component (see Par.[0023] wherein one or more of the dies 102 may be logic dies (e.g., silicon-based dies), and one or more of the dies 102 may be memory dies (e.g., high bandwidth memory)).
With respect to claim 12, Pietambaram discloses, in Figs.1-22, the semiconductor device, wherein the third layer (112, 114) comprises a glass material, a ceramic material, a diamond material, or a silicon material (see Par.[0027]-[0030] wherein an assembly that includes a glass core 114; see Par.[0018] wherein the metallization regions 112 may include a dielectric material 108 and conductive material 116, with the conductive material 116 arranged in the dielectric material 108 (e.g., in lines and vias, as shown) to provide conductive pathways through the metallization regions 112).
With respect to claim 14, Pietambaram discloses, in Figs.1-22, the semiconductor device, wherein the third layer (112, 114) further comprises a second circuit (104), and the second circuit (104) comprises a memory, a thermal component, a mechanical component, an optical component, or an electrical component (see Par.[0020] wherein a bridge component 104 may be embedded in the metallization region 112-1, and may be electrically coupled to the metallization region 112-1; the bridge component 104 may be a “passive” component in that it does not contain one or more active devices).
With respect to claim 16, Pietambaram discloses, in Figs.1-22, the semiconductor device, wherein the first wiring is coupled to the third layer.
With respect to claim 17, Pietambaram discloses, in Figs.1-22, the semiconductor device, wherein the second thickness is less than or equal to 30 um, and the fourth thickness is less than or equal to 30 um.
With respect to claim 18, Pietambaram discloses, in Figs.1-22, the semiconductor device of claim 10, wherein the third thickness is greater than 100 um and less than 2000 um.
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (US 2022/0302009 A1 hereinafter referred to as “Wu”).
With respect to claim 19, Wu discloses, in Figs.1-22, a semiconductor device being formed by a process, the process comprising: providing a substrate (100, 200), the substrate (100, 200) comprising a first side and a second side (see Par.[0017] wherein a routing substrate 200 (see FIG. 10) has been bonded to each interconnect structure 100; the carrier substrate 102 is a silicon wafer 102A); providing a wafer (102) coupled to the second side (see Par.[0017] wherein a routing substrate 200 (see FIG. 10) has been bonded to each interconnect structure 100; the carrier substrate 102 is a silicon wafer 102A); forming a first via (210) in the substrate (102); forming a first layer (218/219) coupled to the first via (210); forming a second layer (208/209) coupled to the first layer (219), the second layer (112) comprising a metal material (see Par.[0043]-[0044] wherein the routing substrate 200 may have one or more routing structures 212/213 formed on each side of the core substrate 202 and through vias 210 extending through the core substrate 202; the routing structures 212/213 may include one or more routing layers 208/209 and one or more dielectric layers 218/219; the routing layers 208/209 and/or through vias 210 comprise one or more layers of copper, nickel, aluminum, other conductive materials, the like, or a combination thereof); forming a third layer (202) coupled to the first side, the third layer comprising a first dielectric material (see Par.[0042]-[0043] wherein he core substrate 202 may include a material such as Ajinomoto build-up film (ABF), a pre-impregnated composite fiber (prepreg) material, an epoxy, a molding compound, an epoxy molding compound, fiberglass-reinforced resin materials, printed circuit board (PCB) materials, silica filler, polymer materials, polyimide materials, paper, glass fiber, non-woven glass fabric, glass, ceramic, other laminates, the like, or combinations thereof); forming a first wiring (112) in the third layer, the first wiring comprising a metal material (see Par.[0051]-[0052] wherein the external connectors 308 make physical and electrical connection to the interconnect structure 100, such as contacting the RDL 112A exposed by the openings 306); forming a fourth layer (218/219) coupled to the first layer (218/219), the fourth layer comprising a first connection (112); and detaching the wafer (102) from the second side (see Par.[0050] wherein turning to FIG. 13, the carrier substrate 102 is de-bonded to detach (or “de-bond”) the carrier substrate 102 from the interconnect structure 100).
With respect to claim 20, Wu discloses, in Figs.1-22, the semiconductor device, wherein the process further comprising embedding a circuit (120, 322, 410) in the substrate (100, 200).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818