DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US PG Pub 2013/0093097, hereinafter Yu).
Regarding claim 1, figures 37-46 of Yu disclose a method for manufacturing a semiconductor device, the method comprising:
forming a substrate; and
coupling a first circuit (174) to the substrate, the first circuit being characterized by a first coefficient of thermal expansion, the substrate being characterized by a second coefficient of thermal expansion (¶ 42),
wherein forming the substrate comprises:
providing a base layer (140), the base layer comprising a first side and a second side;
coupling a first wafer (158) to the second side;
forming a first via (148) in the base layer;
depositing a first layer (162) on the first side, the first layer comprising a first dielectric material (¶ 48);
forming a first wiring (164) in the first layer;
depositing a second layer (166) on the first layer; and
forming a first connection (176) in the second layer, the first circuit being coupled to the substrate via the first connection.
Yu does not explicitly disclose a ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is greater than or equal to 3:5.
However, Yu discloses that the first circuit and substrate are formed of similar materials in order to minimize a CTE mismatch (¶ 42).
Thus, it is obvious to form the device such that a ratio of the first CTE to the second CTE is close to 1:1 (which would meet the limitation “greater than or equal to 3:5”) for the purpose of minimizing the CTE mismatch).
Furthermore, the ordinary artisan would have recognized the material and to be a result effective variable affecting the relative CTE ratios. Thus, it would have been obvious to choose materials that satisfy relative CTE ratios within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Regarding claim 2, figures 37-46 of Yu disclose the first connection (176) comprises a conductive pad.
Regarding claim 3, figures 37-46 of Yu disclose the first connection (176) comprises a metal bump.
Regarding claim 4, figures 37-46 of Yu disclose the substrate is characterized by a first thickness;
the base layer (140) is characterized by a second thickness; and
the second thickness is greater than 60% of the first thickness.
Furthermore, it would have been obvious to form the base layer with a thickness within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 5, figures 37-46 of Yu disclose the base layer comprises a glass material, a ceramic material, a diamond material, or a silicon material (¶ 42).
Regarding claim 6, figures 37-46 of Yu disclose depositing a third layer (144) on the substrate, the third layer being coupled to the first via (148).
Regarding claim 7, figures 37-46 of Yu disclose the third layer (144) comprises a titanium nitride material, a tungsten material, a silicon oxide material (¶ 43), or a copper material.
Regarding claim 8, figures 37-46 of Yu disclose the first dielectric material (of layer 162) comprises a polyimide material or a silicon nitride material (¶ 46, 48).
Regarding claim 9, figures 37-46 of Yu disclose the second layer (166) comprises a passivation material (¶ 46, 48).
Regarding claim 10, figures 46-49A of Yu disclose coupling a second wafer (202) to the second layer (166); and
detaching the first wafer (158) from the base layer.
Regarding claim 11, figure 53 of Yu discloses a fourth layer (154) on the second side, the fourth layer comprising a second dielectric material (¶ 46).
Regarding claim 12, figure 53 of Yu discloses the second dielectric material is different from the first dielectric material (¶ 46).
Regarding claim 13, figure 53 of Yu discloses a second wiring (152) in the fourth layer, the second wiring comprising a metal material (¶ 46).
Regarding claim 19, figures 37-46 of Yu disclose a method for manufacturing a semiconductor device, the method comprising:
providing a base layer (140), the base layer comprising a first side and a second side;
coupling a first wafer (158) to the second side;
forming a first via (148) in the base layer;
depositing a first layer (162) on the first side, the first layer comprising a first dielectric material (¶ 48);
forming a first wiring (164) in the first layer; and
depositing a second layer (166) on the first layer.
Claims 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Paital et al. (US PG Pub 2023/0085411, hereinafter Paital).
Regarding claim 14, figures 37-46 of Yu disclose a method for manufacturing a semiconductor device, the method comprising:
forming a substrate; and
coupling a first circuit (174) to the substrate, the first circuit being characterized by a first coefficient of thermal expansion, the substrate being characterized by a second coefficient of thermal expansion (¶ 42),
wherein forming the substrate comprises:
providing a base layer (140), the base layer comprising a first side and a second side;
coupling a first wafer (158) to the second side;
forming a first via (148) in the base layer;
depositing a first layer (162) on the first side, the first layer comprising a first dielectric material (¶ 48);
forming a first wiring (164) in the first layer;
depositing a second layer (166) on the first layer; and
forming a first connection (176) in the second layer, the first circuit being coupled to the substrate via the first connection.
Yu does not explicitly disclose a ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is greater than or equal to 3:5.
However, Yu discloses that the first circuit and substrate are formed of similar materials in order to minimize a CTE mismatch (¶ 42).
Thus, it is obvious to form the device such that a ratio of the first CTE to the second CTE is close to 1:1 (which would meet the limitation “greater than or equal to 3:5”) for the purpose of minimizing the CTE mismatch).
Furthermore, the ordinary artisan would have recognized the material and to be a result effective variable affecting the relative CTE ratios. Thus, it would have been obvious to choose materials that satisfy relative CTE ratios within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Yu does not explicitly disclose forming a cavity in the base layer, the cavity being positioned on the first side;
embedding a second circuit in the cavity.
In the same field of endeavor, figures 4A-4J of Paital disclose forming a cavity (106) in a base layer (400), the cavity being positioned on a first side; and
embedding a second circuit (108) in the cavity.
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form a cavity in the base layer, the cavity being positioned on the first side; and embed a second circuit in the cavity as taught by Mo for the purpose of reducing package dimensions and increasing device density (¶ 14).
Regarding claim 15, Paital discloses the second circuit (108) comprises a memory, a thermal component, a mechanical component, an optical component, or an electrical component (¶ 67).
Regarding claim 16, figures 37-46 of Yu disclose the substrate is characterized by a first thickness;
the base layer (140) is characterized by a second thickness; and
the second thickness is greater than 60% of the first thickness.
Furthermore, it would have been obvious to form the base layer with a thickness within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 17, figures 37-46 of Yu disclose the first layer (162) is characterized by a third thickness.
Yu does not explicitly disclose the third thickness is less than or equal to 30 µm.
However, it would have been obvious to form the first layer with a thickness within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 18, figures 37-46 of Yu disclose the base layer (140) comprises a glass material, a ceramic material, a diamond material, or a silicon material (¶ 42).
Regarding claim 20, Yu does not explicitly disclose embedding a circuit in the base layer (140).
In the same field of endeavor, figures 4A-4J of Paital disclose embedding a second circuit (108) in a base layer (400).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to embed a circuit in the base layer as taught by Mo for the purpose of reducing package dimensions and increasing device density (¶ 14).
Conclusion
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/YU-HSI D SUN/Primary Examiner, Art Unit 2817