DETAILED ACTION
The RCE filed February 27, 2026 has been entered. Claims 1-20 are pending. Claims 1, 9 and 16 are independent.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-12 and 15-18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Fai et al. (US 2013/0297852) in view of Park (US 2017/0154666).
Regarding independent claim 1, Fai et al. teach a memory device (see FIG. 1), comprising:
a first memory die (112a) including a first charge pump (130a) and a first pump control circuit (128a along with FIG. 3B: 340b, and e.g., para. 0049); and
a second memory die (112b) including a second charge pump (130b) coupled to the first charge pump through a pump line (124) and a second pump control circuit (128b along with FIG. 3B: 340b) coupled to the first pump control circuit through a control line (126),
wherein the first pump control circuit is configured to control the first charge pump to perform a pump operation of generating a pump voltage in response to a command received by the first memory die, and is configured to output an operation alarm signal through the control line (FIG. 1 along with FIGS. 3A-B, and accompanying disclosure), and
wherein the second pump control circuit is configured to control the second charge pump to perform the pump operation in response to the operation alarm signal (FIG. 1 along with FIGS. 3A-B, and accompanying disclosure).
Fai’s controller generates and outputs commands to the charge pumps does not clearly explain the claimed limitation, “generates and outputs an operation alarm signal through the control line based on a result comparing a reference voltage with a pump voltage output from the first charge pump”.
Park teaches the deficiencies in FIGS. 2 or 4, and accompanying disclosure, e.g., para. 0045: In an embodiment, the detector 150 is configured to detect whether a level of an output voltage of each of the charge pumps 156 to 158 is lower than that of a reference voltage or not. The detector 150 may output an up/down signal (UP/DN) as the detected result. In an embodiment, the detector 150 is implemented by a comparator. The UP signal indicates that the output voltage is higher than the reference voltage and the DN signal indicates that the output voltage is lower than the reference voltage.
Fai and Park are analogous art because they both are directed to charge pump device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fai with the specified features of Park because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Park to the teaching of Fai et al. such that a memory, as taught by Fai et al., utilizes a control signal to the first and second charge pumps, as taught by Park, for the purpose of achieving enhanced power supply voltages to the memory devices.
Regarding claim 2, Fai et al. and Park, as combined, teach the limitations of claim 1.
Fai et al. further teach each of the first charge pump and the second charge pump outputs the pump voltage to the pump line (FIG. 3B).
Regarding claim 3, Fai et al. and Park, as combined, teach the limitations of claim 1.
Fai et al. further teach the first memory die further comprises a first control logic circuit configured to activate (e.g., para. 0026: … charge pumps are activated deactivated for each access request received at an NVM die …) a pump enable signal in response to the command, the first control logic circuit coupled to the first pump control circuit, and the first pump control circuit configured to provide a pump operation signal instructing the pump operation to be performed by the first charge pump in response to an activated pump enable signal (see FIG. 1 along with FIGS 3A-B and accompanying disclosure).
Fai et al’ activation and deactivation of each charge pump do not explicitly note a pump enable signal.
However, enable signals that control the activation and deactivation of logic are well-known technology for a type of controlling circuit for its purpose.
For support, of the above asserted facts, see for example, Suzuki, e.g., FIG. 6: S1, S2 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize enable signals controlling activation and deactivation in programmable integrated circuits because these conventional technology are well established in the art of the memory devices.
Regarding claim 4, Fai et al. and Park, as combined, teach the limitations of claim 1.
Fai et al. further teach the second memory die further comprises a second control logic circuit configured to provide a deactivated pump enable signal (e.g., para. 0026: … charge pumps are activated deactivated for each access request received at an NVM die …) to the second pump control circuit, and the second pump control circuit configured to provide a pump operation signal instructing the pump operation to be performed by the second charge pump based on the deactivated pump enable signal and the operation alarm signal (see FIG. 1 along with FIGS 3A-B and accompanying disclosure).
Regarding claim 8, Fai et al. and Park, as combined, teach the limitations of claim 1.
Fai et al. further teach an address decoder configured to provide the operating voltage to at least one word line (para. 0033: … address to one of NVM …, further decoder logic to active one of word line is an inherent characteristic in memory address logic).
Fai et al. are silent with respect to the first memory die further comprises: a regulator configured to regulate the pump voltage as an operating voltage.
However, a regulator in voltage supplying components such as claimed charge pump, PMIC, etc. is a well-known technology for a type of semiconductor voltage control device for its purpose.
For support, of the above asserted facts, see for example, Suzuki (US 2023/0062829), e.g., FIG. 6: RE1.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Suzuki to the teaching of Fai et al. and Park, as combined, such that a memory, as taught by Fai et al. and Park, utilizes a voltage regulator, as taught by Suzuki, for the purpose of supplying stable power supply to memory device (see Suzuki, para. 0113), thereby enhancing memory operations.
Regarding independent claim 9, Fai et al. teach a memory device (see FIG. 1), comprising:
a first memory die (112a) including a first pump control circuit (128a along with FIG. 3B: 340b, and e.g., para. 0049), a first charge pump (130a), and a first regulator; and
a second memory die (112b) including a second pump control circuit (128b along with FIG. 3B: 340b, and e.g., para. 0049) coupled in common (126) to the first pump control circuit, a second charge pump (130b), and a second regulator coupled in common to the first regulator,
wherein the first pump control circuit drives the first charge pump based on a pump enable signal activated in response to a command received by the first memory die, and outputs an operation alarm signal (e.g., FIG. 5: 507, for each multi-access request, transmit a command; i.e., “a command” which is claimed “an operation alarm signal”), indicating that the first charge pump is operating, to the second pump control circuit (FIGS. 1-2 along with FIGS. 4-5, and accompanying disclosure), and
wherein the second pump control circuit drives the second charge pump in response to the operation alarm signal (FIGS. 1-2 along with FIGS. 4-5, and accompanying disclosure).
Fai et al. are silent with respect to a regulator.
However, a regulator in voltage supplying components such as claimed charge pump, PMIC, etc. is a well-known technology for a type of semiconductor voltage control device for its purpose.
For support, of the above asserted facts, see for example, Suzuki, e.g., FIG. 6: RE1 in 10_0 coupled to RE1 in 10_1.
Fai’s controller generates and outputs commands to the charge pumps does not clearly explain the claimed limitation, “generates and outputs an operation alarm signal through the control line based on a result comparing a reference voltage with a pump voltage output from the first charge pump”.
Park teaches the deficiencies in FIGS. 2 or 4, and accompanying disclosure, e.g., para. 0045: In an embodiment, the detector 150 is configured to detect whether a level of an output voltage of each of the charge pumps 156 to 158 is lower than that of a reference voltage or not. The detector 150 may output an up/down signal (UP/DN) as the detected result. In an embodiment, the detector 150 is implemented by a comparator. The UP signal indicates that the output voltage is higher than the reference voltage and the DN signal indicates that the output voltage is lower than the reference voltage.
Fai and Park are analogous art because they both are directed to charge pump device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fai with the specified features of Park because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Park to the teaching of Fai et al. such that a memory, as taught by Fai et al., utilizes a control signal to the first and second charge pumps, as taught by Park, for the purpose of achieving enhanced power supply voltages to the memory devices.
Regarding claim 10, Fai et al and Park, as combined, teach the limitation of claim 9.
Park further teaches each of the first charge pump and the second charge pump performs a pump operation of generating a pump voltage, and each of the first regulator and the second regulator outputs an operating voltage obtained by regulating the pump voltage to a regulator line coupled in common to the first and second regulators (e.g., FIGS. 2 or 4, and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Park for the same purpose of supplying stable power supply to memory device.
Regarding claim 11, Fai et al and Park, as combined, teach the limitation of claim 9.
Fai et al. further teach the first memory die further comprises: a first control logic circuit configured to activate the pump enable signal in response to the command received from a memory controller (FIG. 1 and accompanying disclosure).
Regarding claim 12, Fai et al and Park, as combined, teach the limitation of claim 9.
Fai et al. further teach the second pump control circuit receives a deactivated pump enable signal (e.g., para. 0026: … charge pumps are activated deactivated for each access request received at an NVM die …).
Regarding claim 15, Fai et al and Park, as combined, teach the limitation of claim 10.
Fai et al.’ FIG. 1 and Suzuki’s FIG. 6 further teach the first memory die performs an operation corresponding to the command based on the operating voltage.
Regarding independent claim 16, Fai et al. teach a memory device (see FIG. 1), comprising:
a plurality of charge pumps (120a-n) coupled to each other in common through a pump line (124); and
a plurality of pump control circuits (128a-n, see also FIGS. 3A-B) coupled to each other in common through a control line (126), and configured to control respective pump operations of the plurality of charge pumps (e.g., para. 0026: … charge pumps are activated deactivated for each access request received at an NVM die …),
wherein a first pump control circuit among the plurality of pump control circuits controls a first charge pump among the plurality of charge pumps to perform the pump operation in response to a pump enable signal, and outputs an operation alarm signal to the control line (FIG. 1 along with FIGS. 3A-B, and accompanying disclosure),
wherein remaining pump control circuits among the plurality of pump control circuits control remaining charge pumps among the plurality of charge pumps to perform respective pump operations in response to the operation alarm signal, and wherein the plurality of charge pumps and the plurality of pump control circuits are included in different memory dies, respectively (FIG. 1 along with FIGS. 3A-B, and accompanying disclosure).
Fai et al’ activation and deactivation of each charge pump do not explicitly note a pump enable signal.
However, enable signals that control the activation and deactivation of logic are well-known technology for a type of controlling circuit for its purpose.
For support, of the above asserted facts, see for example, Suzuki (US 2023/0062829), e.g., FIG. 6: S1, S2 and accompanying disclosure.
Fai’s controller generates and outputs commands to the charge pumps does not clearly explain the claimed limitation, “generates and outputs an operation alarm signal through the control line based on a result comparing a reference voltage with a pump voltage output from the first charge pump”.
Park teaches the deficiencies in FIGS. 2 or 4, and accompanying disclosure, e.g., para. 0045: In an embodiment, the detector 150 is configured to detect whether a level of an output voltage of each of the charge pumps 156 to 158 is lower than that of a reference voltage or not. The detector 150 may output an up/down signal (UP/DN) as the detected result. In an embodiment, the detector 150 is implemented by a comparator. The UP signal indicates that the output voltage is higher than the reference voltage and the DN signal indicates that the output voltage is lower than the reference voltage.
Fai and Park are analogous art because they both are directed to charge pump device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fai with the specified features of Park because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Park to the teaching of Fai et al. such that a memory, as taught by Fai et al., utilizes a control signal to the first and second charge pumps, as taught by Park, for the purpose of achieving enhanced power supply voltages to the memory devices.
Regarding claim 17, Fai et al and Park, as combined, teach the limitation of claim 16.
Fai et al. further teach the pump enable signal is activated in response to a command received by a memory die including the first pump control circuit and the first charge pump (e.g., para. 0026: … charge pumps are activated deactivated for each access request received at an NVM die …).
Regarding claim 18, Fai et al and Park, as combined, teach the limitation of claim 16.
Fai et al. further teach a pump enable signal coupled to each of the remaining pump control circuits is in a deactivated state (e.g., para. 0026: … charge pumps are activated deactivated for each access request received at an NVM die …; i.e., a consecutive access requests implies one circuit activated and the remaining circuits are not in a activated state).
Allowable Subject Matter
Claims 5-7, 13-14 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s RCE filed 02/27/2026, with respect to the rejection(s) of claims 1-20 under 35 USC 102 and 103, have been fully considered, but are moot in view of the new ground(s) of rejection. Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
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