DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election of group I, claims 1-11 without traverse is acknowledged. Claims 12-20 are withdrawn from considerations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-8 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2005/0224861), (hereinafter, Lee).
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RE Claim 1, Lee discloses in FIGS. 1-9 an isolation-less non-volatile memory structure, including plurality of memory cells and a method of making the same. Lee discloses a structure for a memory device, comprising:
a memory cell, the memory cell comprising a first electrode 22a and a second electrode 22a. examiner notes that 22a/22b are part of a floating gate and functionally equivalent to first and second electrodes; and
a transistor adjacent to the memory cell, the transistor comprising a gate electrode 66 “control gate” including an upper section and a lower section, referring to annotated FIG. 3a above, a third electrode 20 “buried source line” under the gate electrode 66, and the second electrode 16b. Examiner notes that the upper section of the control gate 66 is mostly horizontal while the lower section is mostly vertical,
wherein the second electrode 22b is above the third electrode 20 “buried source line” and laterally adjacent to the lower section of the gate electrode 66.
RE Claim 2, Lee discloses a structure, wherein the second electrode 22b is partially under the upper section of the gate electrode 66.
RE Claim 5, Lee discloses a structure, wherein the first electrode 22a partially overlaps a corner of the second electrode 22b distal from the gate electrode 66, referring to the annotated FIG. 3a.
RE Claim 6, Lee discloses a structure, wherein the transistor further comprises:
a channel layer partially overlapping the second electrode 22b. examiner notes that the channel is disposed along the planar surface 52 between the bit line 16 and the trench 58 [0055]; and
a dielectric layer 64 over the channel layer, referring to FIG. 4d, wherein the channel layer and the dielectric layer are concentric around the lower section of the gate electrode 66 [0055].
RE Claim 7, Lee discloses a structure, wherein the memory cell further comprises the dielectric layer 64 between the first electrode 22a and the second electrode 22b.
RE Claim 8, Lee discloses a structure, wherein the dielectric layer 64 is a resistive layer of the memory cell. First, examiner notes that recitation of “is a resistive layer of the memory cell” is an intended use language that does not result in a structural difference between the claimed invention and the prior art, thus claimed invention is only an art recognized suitability for an intended purpose, MPEP 2144.07. Furthermore, dielectric layers such as the silicon oxide layer 63 of Lee’s disclosure although acts as an insulator, it can temporarily resist or store an electric field. Under specific conditions (like high voltages or specific frequencies), it can behave like a resistive layer by dissipating electrical energy. This occurs due to electrical leakage, polarization, or dielectric breakdown. The instant disclosure point at dielectric materials such as tantalum oxide, titanium oxide, hafnium oxide, aluminum oxide, or silicon oxide as resistive layers, silicon oxide dielectric layer 64 of Lee is consistent functionally with claimed limitation.
RE Claim 11, Lee discloses a structure, wherein the second electrode 22b extends to opposite sides of the gate electrode 66, referring to FIG. 3a.
Allowable Subject Matter
Claims 3-4 and 9-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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