DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending in the application and are examined on merits herein.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 10 of the current application are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1, 5, 12, and 15 of copending Application No. 17/755871. Although the claims at issue are not identical, they are not patentably distinct from each other because one of ordinary skill in the art before the effective date of filing the application by combining Claims 1 and 5 and Claims 12 and 15 of 17755871 could come up with all limitations of Claims 1 and 10 of 18/496,866 limitations, as is shown in a Table of Comparison below:
Table of Comparison
18/496,899: claim number
17/755,871: claim number
Differences and Obviousness of combining limitations to come up with claims of 18/496,899
1
1
Claim 1 of 17/755,871 teaches most limitations of Claim 1 of the current application (directed to an array substrate), except for two limitations: “a source drain layer disposed on the substrate, wherein the source-drain layer comprises a source contact portion and a drain contact portion separated from each other” and: “the first active layer directly contacts the source contact portion and the drain contact portion”. However, Claim 5 of 17/755,871 has the above-cited limitations (but “names” “contact portions” – as “electrodes”). It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to combine Claims 1 and 5 of 17/755,871, since cited by Claim 1 – the gate, the active layer, and the channel – are parts of a transistor that inherently comprises a source-drain layer, and adding source and drain electrodes to the source-drain layer is appropriate for providing external connections to the transistor.
As such, a combination of Claims 1 and 5 of 17/755,871 teaches all limitations of Claim 1 of the current application.
10
12
Claim 10 of 18/496,899 (directed to a display panel, and incorporating all limitations of Claim 1) differs from Claim 12 of 17/755,871 by having extra limitations (of Claim 1), such as: “a source drain layer disposed on the substrate, wherein the source-drain layer comprises a source contact portion and a drain contact portion separated from each other” and: “the first active layer directly contacts the source contact portion and the drain contact portion”). However, Claim 15 of 17/755,871 has limitations that are “absent” from Claim 12, but using words: “source electrode” and “drain electrode”, instead of: “source contact” and “drain contact”. It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to combine Claims 12 and 15 of 17/755,871, because cited by Claim 12 – the gate, the active layer, and the channel – are parts of a transistor that inherently comprises a source-drain layer, while adding source and drain electrodes is appropriate for providing external connections to the claimed transistor of the display.
As such, a combination of Claims 12 and 15 of 17/755,871 teaches all limitations of Claim 10 of the current application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo (CN 114823914). In order to avoid mistakes of a machine translation, in the current Office Action, references to CN 114823914 would be made, instead, to its USA analog US 2024/0153959.
In re Claim 1, Luo teaches an array substrate (Title, Abstract), comprising (Figs. 1-3):
a substrate 110 (paragraph 0033);
a first active layer 140 disposed on the substrate 110 and comprising a first channel portion 141 (paragraphs 0033-0034);
a source-drain layer disposed on the substrate, wherein the source-drain layer and the first channel portion are disposed on a surface of a same layer, and
the source-drain layer 120 comprises a source contact portion 121 and a drain contact portion 122 separated from each other (paragraph 0049-0050);
a first gate 160/150 (paragraph 0042) disposed on one side (e.g., on a top side) of the first active layer 140 away from the substrate 110, wherein the first gate 160/150 is disposed corresponding to the first channel portion 141;
a second active layer 180 disposed on one side of the first gate 160/150 away from the substrate 110, wherein the second active layer 180 comprises a second channel portion 181 (paragraph 0035), and
the first channel portion 141 and the second channel portion 181 are separated from each other; and
a second gate 210/190 (paragraphs 0045-0046) disposed on one side of the second active layer 180 away from the substrate 110, wherein the second gate 210/190 is disposed corresponding to the second channel portion 181; wherein
the first active layer 140 and the second active layer are 180 connected in parallel (Abstract, paragraph 0035), and
the first active layer 140 directly contacts the source contact portion 121 and the drain contact portion 122 (as shown).
In re Claim 10, Luo teaches a display panel, comprising the array substrate as claimed in Claim 1 and (Figs. 1-3) also comprising a light-emitting component disposed on one side of the array substrate, wherein the array substrate and the light- emitting component are combined into a single unit (e.g., “in one body”, paragraphs 0018, 0063, 0072).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5, 6, 11, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Li et al. (US 2024/0222379).
In re Claim 2, Luo teaches the array substrate according to Claim 1 as cited above, including the first and second active layers and the first and second channel portions.
Luo does not teach that the first active layer comprises two first doped portions disposed on two sides of the first channel portion, does not teach that the second active layer comprises two second doped portions disposed on two sides of the second channel portion; does not teach that the first channel portion is disposed between the source contact portion and the drain contact portion; the two first doped portions make electrical contact with the source contact portion and the drain contact portion, respectively, where the second doped portions are electrically connected to the respectively corresponding first doped portions through first via holes.
However, Luo, not teaching that his source and drain regions are doped, teaches that source and drain regions of the first active layer 140 are electrically connected to source and drain regions of the second active layer 180 though first via holes (Fig. 1-3, paragraph 0043)
Li teaches an array substrate (Title, Abstract) comprising a transistor having (Fig. 1)
a first active layer that comprises two first doped portions 312 disposed on two sides of a first channel portion 313 (paragraph 0072);
a second active layer that comprises two second doped portions 317 disposed on two sides of a second channel portion 323 (paragraph 0072);
the first channel portion 313 is disposed between a source contact portion - left 311 - and a drain contact portion – right 311 (paragraph 0075);
the two first doped portions 312 (left and right) make electrical contact with the source contact portion 311 (left) and the drain contact portion 311 (right), respectively; and
the second doped portions 317 are electrically connected to the respectively corresponding first doped portions 312 through first via holes 250 and 251 (paragraph 0079).
Luo and Li teach analogous arts directed to an array substrate comprised a transistor with a stack of two active layers that are connected to each other in parallel through vias disposed in via holes, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Luo device in view of the Li device, since they are from the same field of endeavor, and Li created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Luo device per Li creating it’s the first active layer to comprise two first doped portions disposed on two sides of the first channel portion, by creating the second active layer to comprise two second doped portions disposed on two sides of the second channel portion, wherein the first channel portion would be disposed between the source contact portion and the drain contact portion and the two first doped portions would make electrical contact with the source contact portion and the drain contact portion, respectively, and where the second doped portions are electrically connected to the respectively corresponding first doped portions through first via holes, when it is desirable creating each of the first and second active layers comprising doped regions at each side of the channel, as it is common in the art. In addition, such modification would reduce a contact resistance between the source/drain layer and the first active layer, allowing, accordingly, to reduce power losses on these contacts.
In re Claim 5, Luo/Li teaches the array substrate according to Claim 2 as cited above, including the first doped portions as directed to source and drain regions of the first active layer.
Luo teaches that the array substrate further comprising a pixel electrode 230 (Figs. 1-3, paragraph 0048), wherein the pixel electrode 230 is electrically connected to the first doped portion on the drain contact portion 122 through a second via hole 171 (paragraph 0043).
Luo further teaches that the pixel electrode 230 and the second gate 210/190 are disposed on a surface of a same layer 182.
In re Claim 6, Luo/Li teaches the array substrate according to Claim 5 as cited above.
Luo/Li does not teach that in a direction from the source contact portion 121 to the drain contact portion 122, a width of the source contact portion is less than a width of the drain contact portion – Lou shows in Figs. 1-3 – an opposite ratio of widths.
However, it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Luo/Li device by reversing contact portions 121 and 122, when it is desirable to have a contact portion under the drain region being wider than a contact portion under the source region: It has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art: In re Gazda, 219 F.2d 449, 104 USPQ 400 (CCPA 1955) (MPEP2144.04.VI.A), and, accordingly, it is not patentable.
In re Claim 11, Luo teaches the display panel according to Claim 10 as cited above. including the first and second active layers and the first and second channel portions, but does not teach that the first active layer comprises two first doped portions disposed on two sides of the first channel portion; does not teach that the second active layer comprises two second doped portions disposed on two sides of the second channel portion; does not teach that the first channel portion is disposed between the source contact portion and the drain contact portion, where the two first doped portions make electrical contact with the source contact portion and the drain contact portion, respectively; and the second doped portions are electrically connected to the respectively corresponding first doped portions through first via holes.
However, Luo, not teaching that his source and drain regions are doped, teaches that source and drain regions of the first active layer 140 are electrically connected to source and drain regions of the second active layer 180 though first via holes (Fig. 1-3, paragraph 0043)
Li teaches an array substrate (Title, Abstract) comprising a transistor having (Fig. 1)
a first active layer that comprises two first doped portions 312 disposed on two sides of a first channel portion 313 (paragraph 0072);
a second active layer that comprises two second doped portions 317 disposed on two sides of a second channel portion 323 (paragraph 0072);
the first channel portion 313 is disposed between a source contact portion - left 311 - and a drain contact portion – right 311 (paragraph 0075);
the two first doped portions 312 (left and right) make electrical contact with the source contact portion 311 (left) and the drain contact portion 311 (right), respectively; and
the second doped portions 317 are electrically connected to the respectively corresponding first doped portions 312 through first via holes 250 and 251 (paragraph 0079).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Luo device per Li creating it’s the first active layer to comprise two first doped portions disposed on two sides of the first channel portion, by creating the second active layer to comprise two second doped portions disposed on two sides of the second channel portion, wherein the first channel portion would be disposed between the source contact portion and the drain contact portion and the two first doped portions would make electrical contact with the source contact portion and the drain contact portion, respectively, and where the second doped portions are electrically connected to the respectively corresponding first doped portions through first via holes, when it is desirable creating each of the first and second active layers comprising doped regions at each side of the channel, as is common in the art. In addition, such modification would reduce a contact resistance between the source/drain layer and the first active layer, allowing, accordingly, to reduce power losses on these contacts.
In re Claim 14, Luo/Li teaches the array substrate according to Claim 2 as cited above, including the first doped portions as directed to source and drain regions of the first active layer.
Luo teaches that the array substrate further comprising a pixel electrode 230 (Figs. 1-3, paragraph 0048), wherein the pixel electrode 230 is electrically connected to the first doped portion on the drain contact portion 122 through a second via hole 171 (paragraph 0043).
Luo further teaches that the pixel electrode 230 and the second gate 210/190 are disposed on a surface of a same layer 182.
Claim 15, Luo/Li teaches the display panel according to Claim 14 as cited above.
Luo/Li does not teach that in a direction from the source contact portion 121 to the drain contact portion 122, a width of the source contact portion is less than a width of the drain contact portion – Lou shows in Figs. 1-3 – an opposite ratio (though Luo does not state anywhere that drawings are in scale).
However, it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Luo/Li device by reversing parts 121 and 122, when it is desirable to have a contact portion under the drain region larger than a contact portion under the source region: It has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art: In re Gazda, 219 F.2d 449, 104 USPQ 400 (CCPA 1955) (MPEP2144.04.VI.A)
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Luo/Li in view of Lee et al. (US 2020/0052001).
In re Claim 9, Luo/Li teaches the array substrate according to Claim 2 as cited above.
Luo further teaches (Figs. 1-3) that in a direction from the source contact portion to the drain contact portion, a length of the first channel portion is larger than a width of the first gate.
Luo/Li does not teach that the length of the first channel portion is less than or equal to a width of the first gate.
Lee teaches (Fig. 2, paragraph 0037) that a width of a channel portion is equal to a width of the gate.
Luo/Li and Lee teach analogous arts directed to array substrate transistors, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Luo/Li device in view of the Lee device, since they are from the same field of endeavor, and Lee created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Luo device such that the width of the first gate would be equal to the length of the first channel, when such modification allows to reduce power consumption of the device (Lee, paragraph 0007).
In re Claim 18, Luo/Li teaches the display panel according to Claim 11 as cited above.
Luo further teaches (Figs. 1-3) that in a direction from the source contact portion to the drain contact portion, a length of the first channel portion is larger than a width of the first gate.
Luo/Li does not teach that the length of the first channel portion is less than or equal to a width of the first gate.
Lee teaches (Fig. 2, paragraph 0037) that a width of a channel portion is equal to a width of the gate.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Luo device such that the width of the first gate would be equal to the length of the first channel, when such modification allows to reduce power consumption of the device (Lee, paragraph 0007).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Luo in view of Kitagawa et al. (US 2023/0178561).
In re Claim 19, Luo teaches a manufacturing method of an array substrate, comprising following steps (Figs. 4 and 5A-5H, paragraph 0074):
S10: providing a substrate 110 (Fig. 5A, paragraph 0075);
S20: forming a source-drain layer 120 on the substrate 110 (Fig. 5B, paragraph 0079);
S30: - shown as S20 in Fig, 4 - forming a first active layer 140 on the substrate 110 (Fig. 5C, paragraph 0077);
S40: - shown as S30 in Fig. 4 - sequentially forming a first gate insulating layer 150 and a first gate 160 on the first active layer (Fig. 5D, paragraphs 0089-0090);
S50: forming an interlayer insulating layer 170 on the first gate 150/160 (Fig. 5E, paragraph 0092);
S60: - shown as S40 in Fig. 4 - forming a second active layer 180 (Fig. 5F, paragraph 0099) on the interlayer insulating layer 170;
S70: - shown as S50 in Fig. 4 - forming a second gate insulating layer 190 on the second active layer 180 (Fig. 5G, paragraph 0102); and
S80: - shown as S50 and S70 in Fig. 4 - forming a second gate 210 (Fig. 5G, paragraph 0103) and a pixel electrode 240 (Fig. 5H, paragraph 0110).
Luo does not teach that the pixel electrode is on the second gate insulating layer, since the second gate insulating layer is narrow. However, the Luo pixel electrode 230 is over an extension of the second gate insulating layer 190.
Kitagawa teaches (Fig. 2B, paragraphs 0048-0049) a gate insulating layer 5 being so long that it overlaps not only with a gate electrode GE, but also with a pixel electrode PE that does not overlap a gate electrode.
Luo and Kitagawa teach analogous arts directed to an array substrate comprised transistors with gates, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Luo device in view of the Kitagawa device, since they are from the same field of endeavor, and Kitagawa created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Luo device and method by extending the second gate insulating layer under the pixel electrode, such that the pixel electrode would be disposed on the second gate insulating layer, when desirable. In accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Luo/Kitagawa in view of Luo (US 2023/0024248) – Luo-1, hereafter.
In re Claim 20, Luo/Kitagawa teaches the manufacturing method of the array substrate according to Claim 19 as cited above.
Luo further teaches (Figs. 1-3) that the source-drain layer comprises a source contact portion 121, a drain contact portion 122.
Luo/Kitagawa does not teach that the device (and method) further comprises a first connection terminal, and a second connection terminal disposed separated from each other; and the first connection terminal and the second connection terminal are disposed on one side of the drain contact portion away from the source contact portion.
Luo-1 teaches a substrate array in which (Fig. 8, paragraph) on a side of a drain contact portion 103 of a left transistor, there are a first connection terminal 102 (of a right transistor) and a second connection terminal 103 (of the right transistor) separated from each other, where the first and second connection terminals are disposed on one side of the drain contact portion away from the source contact portion of the left transistor.
Luo/Kitagawa and Luo-1 teach analogous arts directed to array substrate comprised transistors and methods of manufacturing array substrates, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Luo/Kitagawa device and method in view of the Luo-1 device and method, since they are from the same field of endeavor, and Luo-1 created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Luo/Kitagawa device in method in view of the Luo-1 device and method, since they are from the same field of endeavor, and Luo-1 created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Luo/Kitagawa device and method by adding to the Luo/Kitagawa structure the first and second contact terminals separated from each other and disposed on one side of the drain contact portion away from the source contact portion, when the Luo/Kitagawa device (created by the Luo/Kitagawa method of Claim 19) comprises more transistors that are shown for the Luo/Kitagawa device (and method).
Allowable Subject Matter
Claims 3, 7-8, 12-13, and 16-17 contain allowable subject matter, while Claim 4 depends on Claim 3; Claims 3-4, 7-8, and 16-17 are objected to as being dependent on a corresponding rejected base claim, but would be allowed if amended to incorporate all limitations of a corresponding base claim and all intervening claims (corrected for Double Patenting, where applicable).
Reason for Indicating Allowable Subject Matter
Re Claim 3: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 3 as: “an ion concentration of the first doped portion is greater than an ion concentration of the second doped portion”, in combination with all limitations of Claims 2 and 1, on which claim 3 depends.
Re Claim 4: Claim 4 is objected to due to dependency on Claim 3, though its limitation is taught by the referenced prior arts.
Re Claim 7: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 7 as: “one end of the pixel electrode extends into the third via hole and is electrically connected to the first connection terminal”, in combination with other limitations of Claim 7 and with all limitations of Claims 1 and 2 on which Claim 7 depends.
Re Claim 8: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation as: “the source-drain layer further comprises an electrical connecting component disposed between the drain contact portion and the first connection terminal, and the drain contact portion and the first connection terminal are electrically connected through the electrical connecting component”, in combination with other limitations of Claim 8, and with all limitations of Claims 1 and 2, on which Claim 8 depends.
Re Claim 12: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 12 as: “an ion concentration of the first doped portion is greater than an ion concentration of the second doped portion”, in combination with all limitations of Claims 1, 10, and 11, on which Claim 12 depends. Claim 13 depends on Claim 12.
Re Claim 16: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 16 as: “one end of the pixel electrode extends into the third via hole and is electrically connected to the first connection terminal”, in combination with other limitations of Claim 16, and in combination with limitations of Claims 1, 10, 11, and 14, on which Claim 16 depends.
Re Claim 17: The prior arts of record, alone or in combination, fail to anticipate or render obvious such limitation of Claim 17 as: “the source-drain layer further comprises an electrical connecting component disposed between the drain contact portion and the first connection terminal, and the drain contact portion and the first connection terminal are electrically connected through the electrical connecting component’, in combination with other limitations of Claim 17 and with limitations of Claims 1, 10, and 11, on which Claim 17 depends.
The prior arts of record, in addition to the prior arts cited by the current Office Action, also include: Shin (US 2021/0408061), Chen (US 2023/0187559_, and Yeh (Us 2013/0240886).
Conclusion
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 12/17/25