DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on June 24, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-11 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2019/0331972 A1 to Nimura et al. (“Nimura”). As to claim 1, Nimura discloses an electro-optical device comprising: a pixel electrode (15); a transistor (130) corresponding to the pixel electrode (15) and including a semiconductor layer (130a), the semiconductor layer (130a) including: a channel region (130c), a drain region (130d) electrically coupled (¶ 0064, ¶ 0089, ¶ 0156, ¶ 0170) to the pixel electrode (15), and a low-concentration drain region (130e) disposed between the channel region (130c) and the drain region (130d) in plan view; and a light-blocking part (36, 51, 108, 109, 142, 144) electrically coupled (¶ 0064, ¶ 0089, ¶ 0156, ¶ 0170) to the pixel electrode (15) and electrically coupled to the drain region (130d) of the semiconductor layer (130a), the light-blocking part (36, 51, 108, 109, 142, 144) including a first portion (108) that overlaps with the low-concentration drain region (130e) of the semiconductor layer (130a) in plan view (See Fig. 1, Fig. 3, Fig. 15-Fig. 20, ¶ 0050, ¶ 0051, ¶ 0053, ¶ 0054, ¶ 0064, ¶ 0084, ¶ 0088, ¶ 0089, ¶ 0146, ¶ 0156, ¶ 0157, ¶ 0160, ¶ 0168-¶ 0173, ¶ 0176-¶ 0180) (Notes: the limitation “part” is defined as a portion or division of a whole that is separate or distinct; piece, fragment, fraction, or section; constituent, the limitation “portion” is defined as a part of any whole, either separated from or integrated with it, and the limitation “couple” is defined as Electricity a. to join or associate by means of a coupler b. to bring (two electric circuits or circuit components) close enough to permit an exchange of electromagnetic energy by Dictionary.com). As to claim 2, Nimura further discloses wherein the semiconductor layer (130a) further includes a source region (130s), and the channel region (130c) is located between the drain region (130d) and the source region (130s) in plan view (See Fig. 15, Fig. 16, ¶ 0169, ¶ 0173). As to claim 3, Nimura discloses further comprising a substrate (10s), wherein the light-blocking part (36, 51, 108, 109, 142, 144) includes two second portions (144) extending from the first portion (108) toward the substrate (10s), the two second portions (144) located on both sides of the semiconductor layer (130a) as viewed in a first direction, respectively (See Fig. 15, Fig. 16). As to claim 4, Nimura further discloses wherein the light-blocking part (36, 51, 108, 109, 142, 144) includes a third portion (142) joined to the drain region (130d) (See Fig. 16) (Notes: the limitation “join” is defined as to bring together in a particular relation or for a specific purpose, action, etc.; unite by Dictionary.com). As to claim 5, Nimura further discloses wherein the light-blocking part (36, 51, 108, 109, 142, 144) includes a third portion (142) joined to the drain region (130d) and the third portion (142) extends from the first portion (108) toward the substrate (10s), is located between the two second portions (144) as viewed in the first direction, and is joined to the two second portions (144) (See Fig. 15, Fig. 16) (Notes: the limitation “join” is defined as to bring together in a particular relation or for a specific purpose, action, etc.; unite by Dictionary.com). As to claim 6, Nimura discloses further comprising a substrate (10s), wherein the light-blocking part (36, 51, 108, 109, 142, 144) includes a fourth portion (109) disposed between the substrate (10s) and the semiconductor layer (130a) (See Fig. 15). As to claim 7, Nimura discloses further comprising: a pixel relay electrode (49); and a coupling member (between 15 and 49), wherein the pixel relay electrode (49) electrically couples the pixel electrode (15) and the transistor (130), and the coupling member (between 15 and 49) is provided in a contact hole (48) through which the pixel relay electrode (49) and the pixel electrode (15) are electrically coupled (See Fig. 1, Fig. 20, ¶ 0146). As to claim 8, Nimura discloses further comprising: a substrate (10s); a scanning line (103a); and an insulating layer (11d), wherein the transistor (130) further includes a gate electrode (130g), the scanning line (103a) is electrically coupled (¶ 0157) to the gate electrode (130g), the insulating layer (11d) is disposed between the scanning line (103a) and the gate electrode (130g), and the semiconductor layer (130a), the gate electrode (130g), the insulating layer (11d), the scanning line (103a), and the pixel electrode (15) are arranged in this order from the substrate (10s) (See Fig. 15, ¶ 0156, ¶ 0157, ¶ 0173). As to claim 9, Nimura further discloses wherein the light-blocking part (36, 51, 108, 109, 142, 144) includes a portion (142, 144) joined to the semiconductor layer (130a) and the light-blocking part (36, 51, 108, 109, 142, 144) has a proximal light-blocking structure (109) in which a distance to the semiconductor layer (130a) is small (See Fig. 15) (Notes: the limitation “join” is defined as to bring together in a particular relation or for a specific purpose, action, etc.; unite by Dictionary.com). As to claim 10, Nimura discloses an electronic apparatus comprising: the electro-optical device according to claim 1; and a control unit (101, 102) configured to control an operation of the electro-optical device (See Fig. 1, ¶ 0050, ¶ 0051). As to claim 11, Nimura discloses further comprising an insulating layer (11d) covering the transistor (130), wherein the first portion (108) of the light-blocking part (36, 51, 108, 109, 142, 144) is disposed in a recess portion of the insulating layer (11d) (See Fig. 15) (Notes: the recess portion is occupied by the first portion).
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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