DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-10 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2019/0196281 A1 to Oikawa et al. (“Oikawa”). As to claim 1, Oikawa discloses an electro-optical device comprising: a substrate (19, 10); a transistor (30) including a semiconductor layer (31a) and a gate electrode (33a), the semiconductor layer (31a) including a drain region (31c1) to which a pixel potential (to 9a) is applied and extending in a first direction; a scanning line (3a) electrically coupled to the gate electrode (33a); an insulating layer (43, 44) disposed between the scanning line (3a) and the gate electrode (33a); and a light-blocking part (2a, 4a, 431, 432, 441, 442), with a light-blocking property, wherein the semiconductor layer (31a), the gate electrode (33a), the insulating layer (43, 44), the scanning line (3a) are arranged in this order from the substrate (19, 10), the light-blocking part (2a, 4a, 431, 432, 441, 442) surrounds the semiconductor layer (31a) as viewed in the first direction, the light-blocking part (2a, 4a, 431, 432, 441, 442) includes a first portion (4a) disposed at the insulating layer (43, 44), and the pixel potential (to 9a) is applied to the light-blocking part (2a, 4a, 431, 432, 441, 442) (See Fig. 1, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, ¶ 0038, ¶ 0039, ¶ 0040, ¶ 0045, ¶ 0046, ¶ 0048, ¶ 0060, ¶ 0061, ¶ 0063, ¶ 0066, ¶ 0067, ¶ 0069, ¶ 0070, ¶ 0071, ¶ 0081, ¶ 0083) (Notes: the limitation “light-blocking” is met by the materials disclosed in ¶ 0063. Further, the limitation “part” is defined as a portion or division of a whole that is separate or distinct; piece, fragment, fraction, or section; constituent and the limitation “portion” is defined as a part of any whole, either separated from or integrated with it by Dictionary.com). As to claim 2, Oikawa further discloses wherein the semiconductor layer (31a) includes the drain region (31c1), a source region (31b1), a channel region (31g) located between the drain region (31c1) and the source region (31b1) in plan view, and a low-concentration drain region (31c2) located between the drain region (31c1) and the channel region (31g) in plan view and the first portion (4a) overlaps the low-concentration drain region (31c2) in plan view (See Fig. 6, ¶ 0067). As to claim 3, Oikawa further discloses wherein the light-blocking part (2a, 4a, 431, 432, 441, 442) includes two second portions (431, 432) extending from the first portion (4a) toward the substrate (19, 10), the two second portions (431, 432) located on both sides of the semiconductor layer (31a) as viewed in the first direction, respectively (See Fig. 7). As to claim 4, Oikawa further discloses wherein the light-blocking part (2a, 4a, 431, 432, 441, 442) includes a third portion (442) joined to the drain region (31c1) (See Fig. 6). As to claim 5, Oikawa further discloses wherein the light-blocking part (2a, 4a, 431, 432, 441, 442) includes a third portion (442) joined to the drain region (31c1) and the third portion (442) extends from the first portion (4a) toward the substrate (19, 10), is located between the two second portions (431, 432) as viewed in the first direction, and is joined to the two second portions (431, 432) (See Fig. 6, Fig. 7, Fig. 9) (Notes: the limitation “join” is defined as to bring together in a particular relation or for a specific purpose, action, etc.; unite by Dictionary.com). As to claim 6, Oikawa further discloses wherein the light-blocking part (2a, 4a, 431, 432, 441, 442) includes a fourth portion (2a) disposed between the substrate (19, 10) and the semiconductor layer (31a) (See Fig. 6). As to claim 7, Oikawa discloses further comprising: a pixel electrode (9a); a pixel relay electrode (3c); and a coupling member (452), wherein the transistor (30) is provided corresponding to the pixel electrode (9a), the pixel relay electrode (3c) electrically couples the pixel electrode (9a) and the transistor (30), and the coupling member (452) is provided in a contact hole (45c) through which the pixel relay electrode (3c) and the pixel electrode (9a) are electrically coupled (See Fig. 6, ¶ 0070, ¶ 0071). As to claim 8, Oikawa discloses further comprising a pixel electrode (9a) of the pixel potential (to 9a), wherein the semiconductor layer (31a), the gate electrode (33a), the insulating layer (43, 44), the scanning line (3a), and the pixel electrode (9a) are arranged in this order from the substrate (19, 10) (See Fig. 6). As to claim 9, Oikawa further discloses wherein the light-blocking part (2a, 4a, 431, 432, 441, 442) includes a portion (442) joined to the semiconductor layer (31a) and the light-blocking part (2a, 4a, 431, 432, 441, 442) has a proximal light-blocking structure (2a) in which a distance to the semiconductor layer (31a) is small (See Fig. 6, Fig. 8). As to claim 10, Oikawa discloses an electronic apparatus comprising: the electro-optical device according to claim 1; and a control unit (104) configured to control an operation of the electro-optical device (See Fig. 1, ¶ 0038, ¶ 0039).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVID CHEN/Primary Examiner, Art Unit 2815