DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7, and 17 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Degani (US 2007/0215976).
Regarding claim 1, Degani discloses a support substrate for a passive electronic component (Fig.2, numeral 11, [0021]), the support substrate comprising: a semiconductor substrate ([0021]); a charge trap layer (12) on the semiconductor substrate (11), the charge trap later having a higher crystal defect density than the semiconductor substrate ([0012]); and a silicon nitride insulating layer on the charge trap layer, wherein an atomic concentration ratio of N to a total amount of Si and N in the insulating layer is not greater than 45 atom% ([0023]; note: Si3N4 layer).
Regarding claim 2, Degani discloses wherein the semiconductor substrate is a single-crystal Si substrate ([0020]).
Regarding claim 3, Degani discloses wherein the charge trap layer is composed of polycrystalline Si ([0021]).
Regarding claim 7, Degani discloses wherein the atomic concentration ratio of N to the total amount of Si and N in the insulating layer is greater than 44 atoms% and not greater than 45 atoms% ([0023]; note: Si3N4 layer).
Regarding claim 17, Degani discloses a passive electronic component comprising the support substrate according to claim 1 (Abstract).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Degani as applied to claim 1 above, and further in view of Wondrak (US 5, 767, 548).
Regarding claim 4, Degani does not disclose wherein the atomic concentration ratio of N to the total amount of Si and N in the insulating layer is not greater than 44 atoms%.
Wondrak however discloses that composition of the insulating layer could adjusted to optimize the fixed charges in the insulating layer (column 5, lines 12-25).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Degani with Wondrak to have the atomic concentration ratio of N to be in the claimed range for the purpose of optimization of the fixed charges in the insulating layer.
Regarding claim 5, Degani does not disclose wherein a fixed charge within the insulating layer is positive.
Wondrak however discloses wherein a fixed charge within the insulating layer is positive (column 5, lines 12-20).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Degani with Wondrak to have a fixed charge within the insulating layer is positive for the purpose of optimizing electric filed strength (Wondrak, column 5, lines 29-25).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Degani as applied to claim 1 above, and further in view of Hutin (US 2023/0411309).
Regarding claim 8, Degani does not disclose wherein a fixed charge within the insulating layer is negative.
Hutin however discloses wherein a fixed charge within the insulating layer is negative (Fig.8 numeral 25) ([0073]).
It would have been therefore obvious to one of ordinary skill in the art the time the invention was filed to modify Degani with Hutin to have a fixed charge within the insulating layer is negative for the purpose of preventing the formation of a parasitic conduction layer in the semiconductor region (Hutin, Abstract).
Claim(s) 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Degani as applied to claim 1above, and further in view of Stuber (US 2014/0346622).
Regarding claim 18, Degani discloses a semiconductor device, comprising: the support substrate according to claim 1; a first electrode layer (Fig.5, numeral 58) on the support substrate (51); a dielectric film (Fig.5; a layer between (58) and (60)) on the first electrode layer (58); a second electrode layer (60) on the dielectric film; a protective layer (Fig. 5, numeral 63) covering the first electrode layer and the second electrode layer.
Degani does not disclose an outer electrode penetrating the protective layer.
Stuber however discloses an outer electrode (Fig.4, numeral 421) penetrating the protective layer (407).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Degani with Stuber to have an outer electrode penetrating the protective layer for the purpose of forming connection to circuitry (Stuber, [0068]).
Regarding claim 19, Stuber discloses a matching circuit ([0161]).
Regarding claim 20, Stuber discloses a filter circuit ([0161]).
Allowable Subject Matter
Claims 10-16 are allowed.
Claims 6 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonable suggest wherein a combination of a conducting type of the semiconductor substrate and a conducting type of the charge trap layer is p-type and p-type, p-type and n-type, or n-type and p-type as required by claim 6.
The search of the prior art does not disclose or reasonably suggest wherein a combination of a conducting type of the semiconductor substrate and a conducting type of the charge trap layer is n-type and n-type, n-type and p-type, or p-type and n-type as required by claim 9.
The search of the prior art does not disclose or reasonably suggest a second insulating layer on the first insulating layer, wherein a first fixed charge within the first insulating layer and a second fixed charge within the second insulating layer have opposite polarities as required by claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JULIA SLUTSKER/Primary Examiner, Art Unit 2891