DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 10/30/2023 has been considered.
Drawings
The drawings filed on 10/30/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 10/30/2023 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 7, 9, 10, 18 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Hwang (US 2020/0152654).
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Regarding claims 1, 6 and 7, Hwang (US 2020/0152654) discloses: A vertical memory device, comprising:
a lower semiconductor layer (LSP, ¶0048) on a substrate (semiconductor substrate 10, ¶0023) including a first region (CAR, ¶0023) and a second region (CNR, ¶0023);
a cell stacked structure (ST, ¶0026) on the lower semiconductor layer, the cell stacked structure including an insulation layer pattern (ILD, ¶0026) and a gate pattern (EL, ¶0026) that are alternately and repeatedly stacked, wherein the cell stacked structure (ST) extends in a first direction parallel to an upper surface of the substrate (10), and wherein an edge portion in the first direction of the cell stacked structure (ST) is disposed in the second region and has a step portion having a step shape (¶0029);
an etch stop structure (ES, ¶0032) on an upper surface of each of gate patterns (EL) of the step portion of the cell stacked structure, wherein the etch stop structure (ES) includes a first variable resistance pattern (HL is transition metal oxide Hf02, ¶0130) and a mask pattern (41, ¶0041) that are stacked;
a channel structure (CVS, ¶0047) passing through the cell stacked structure (ST) on the first region (CAR), and extending to an inner portion of the lower semiconductor layer (10);
an insulating interlayer (55) covering the cell stacked structure; and
a contact plug (CPLG, ¶0069) passing through the insulating interlayer (55) and the etch stop structure (ES) in the second region (CNR), wherein the contact plug (CPLG) contacts the upper surface of each of the gate patterns (EL) in the second region (CNR).
Regarding claim 9, Hwang further discloses:
wherein the etch stop structure (ES) covers a portion of the upper surface of each of the gate patterns (EL) of the step portion of the cell stacked structure (ST).
Regarding claim 10, Hwang further discloses:
wherein the etch stop structure (ES) is horizontally spaced apart (by pad dielectric 25) from sidewalls of the insulation layer pattern (ILD) and the gate pattern (EL) positioned on the etch stop structure.
Regarding claim 18 Hwang discloses:
A vertical memory device, comprising:
a cell stacked structure (ST) on a substrate (10), wherein the cell stacked structure includes an insulation layer pattern (ILD) and a gate pattern (EL) that are alternately and repeatedly stacked, and wherein the cell stacked structure (ST) extends in a first direction parallel to an upper surface of the substrate, and wherein an edge portion in the first direction of the cell stacked structure is disposed in a second region and has a step portion having a step shape (¶0029);
an etch stop structure (ES) on an upper surface of each of gate patterns (EL) of the step portion of the cell stacked structure (ST), wherein the etch stop structure (ES, HL, includes a transition metal oxide, ¶0130);
an insulating interlayer (55) covering the cell stacked structure; and
a contact plug (CPLG) passing through the insulating interlayer and the etch stop structure, wherein the contact plug contacts the upper surface of each of the gate patterns (EL).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8, 11, 12, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang.
Regarding claim 8, Hwang does not disclose “wherein the contact plug (CPLG) has a first portion extending from an upper surface of the insulating interlayer to a bottom surface of the mask pattern of the etch stop structure and a second portion extending from a bottom of the first portion to an upper surface of the gate pattern, and wherein the second portion has a width greater than a width of the first portion”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Regarding claim 11, the prior art does not disclose “wherein the gate pattern includes polysilicon”. However, It would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to select polysilicon as a gate material, since it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill. In re Leshing, 125 USPQ 416 (CCPA 1960) and Sinclair & Carroll Co. v. Interchemical Corp., 65 USPQ 297 (1945).
Regarding claim 12, Hwang does not disclose “wherein the mask pattern includes silicon nitride”. However, It would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to select silicon nitride as a mask pattern material, since it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill. In re Leshing, 125 USPQ 416 (CCPA 1960) and Sinclair & Carroll Co. v. Interchemical Corp., 65 USPQ 297 (1945).
Regarding claim 20, Hwang discloses:
wherein the contact plug (CPLG) has a first portion that contacts the transition metal oxide (HL) included in the etch stop structure (ES). Hwang does not disclose “wherein the first portion contacting the transition metal oxide of the contact plug has a width greater than a width of a second portion of the contact plug”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Allowable Subject Matter
Claims 13-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, the prior art does not disclose “a cell variable resistance pattern, that are stacked on a sidewall of the channel hole, and wherein the channel is electrically connected to the lower semiconductor layer” and “wherein the cell variable resistance pattern and the first variable resistance pattern include the same material, and wherein a thickness in a horizontal direction of the cell variable resistance pattern on the sidewall of the channel hole is the same as a thickness in a vertical direction of the first variable resistance pattern on the upper surface of the gate patterns” in combination with the remaining claimed features.
Claims 2-5, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the prior art does not disclose “wherein the channel structure is in a channel hole passing through the cell stacked structure, and the channel structure includes a gate insulation layer pattern, a channel, a cell variable resistance pattern, a filling insulation pattern, and an upper pad” in combination with the remaining claimed features.
Regarding claim 19, the prior art does not disclose “a channel structure passing through the cell stacked structure, and wherein the channel structure includes a cell variable resistance pattern including the transition metal oxide.” In combination with the remaining claimed features.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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/WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899