DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 10/30/2023 has been considered.
Drawings
The drawings filed on 10/30/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 10/30/2023 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8 and 13 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Seo (US 2021/0193581).
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Regarding claim 1, Seo discloses:
A semiconductor package (10, ¶0026), comprising:
a redistribution layer structure (140, ¶0027);
a semiconductor structure (110, ¶0027) on the redistribution layer structure;
a printed circuit board (130, ¶0027, ¶0051) on the redistribution layer structure (140) and extending around a side surface of the semiconductor structure 110);
a molding material (163, ¶0027) extending around the semiconductor structure on the redistribution layer structure; and
a silicon interposer (121, ¶0048 discloses 121 and 111 are the same, ¶0034, ¶0035 disclose 111 and 121 are silicon) on the printed circuit board (130) and the molding material (163).
Regarding claim 8, Seo further discloses:
wherein the printed circuit (130) board includes an opening, and the semiconductor structure (110) is within the opening.
Regarding claim 13, Seo further discloses:
wherein the redistribution layer structure (140) includes a plurality of redistribution layer vias (143) , at least a subset of the redistribution layer vias at a level of an uppermost portion of the redistribution layer structure being directly bonded to the semiconductor structure (110).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) s 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo.
Regarding claim 14, Seo does not disclose “wherein each redistribution layer via among the plurality of redistribution layer vias has a width, in a horizontal direction parallel to an upper surface of the redistribution layer structure, of an uppermost portion of the redistribution layer via that is smaller than a width of a lowermost portion of the redistribution layer via”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Claim(s) 3-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo in view of Pagalia (US 8,080,445).
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Regarding claim 3, Seo does not disclose “wherein the silicon interposer includes a plurality of first through silicon vias” in a similar device, however, Pagalia (US 8,080,445) discloses a semiconductor package (160), comprising:
a redistribution layer structure (122), a semiconductor structure (124) on the redistribution layer structure, an interconnect (132) on the redistribution layer structure (140) and extending around a side surface of the semiconductor structure 110), a molding material (140) extending around the semiconductor structure (124) on the redistribution layer structure; and
a silicon interposer (134, column 7 line 60) on the interconnect (132) and the molding material (140). Pagalia discloses a structure as taught provides improved thermal dissipation (column 8 lines 5-30> Therefore it would have been obvious to one having skill in the art before the effective filing date of the claimed invention to modify the device of Seo, including providing wherein the silicon interposer includes a plurality of first through silicon vias in order to provide improved thermal dissipation as taught by Pagalia
Regarding claim 4, Seo further discloses:
wherein the printed circuit board (130) is configured to electrically connect the redistribution layer structure (110) and what would be the plurality of first through silicon vias of Pagalia.
Regarding claim 5, the modification of Pagalia further discloses:
wherein the silicon interposer includes a heat dissipation structure comprising a plurality of second through silicon vias (136a, 136b, column 8 line 26, figure 3i).
Regarding claim 6, the modification of Pagalia further discloses:
wherein each of at least a subset of the plurality of second through silicon vias (136a) are electrically insulated.
Allowable Subject Matter
Claims 2, 7 and 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the prior art does not disclose “2. The semiconductor package of claim 1, wherein a thermal conductivity of the silicon interposer is higher than a thermal conductivity of the redistribution layer structure” in combination with the remaining claimed features.
Regarding claim 7, the prior art does not disclose “wherein the printed circuit board includes an embedded trace substrate (ETS)” in combination with the remaining claimed features.
Regarding claim 9, the prior art does not disclose “wherein the semiconductor structure includes a three dimensional integrated circuit (3D IC) structure including a first semiconductor die and a second semiconductor die on the first semiconductor die” in combination with the remaining claimed features.
Claims 15-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 15, the prior art does not disclose “a conductive adhesive member on the first semiconductor structure” and “a molding material extending around the first semiconductor structure on the redistribution layer structure; a silicon interposer on the conductive adhesive member, the printed circuit board, and the molding material; and a second semiconductor structure on the silicon interposer” in combination with the remaining claimed features.
Regarding claim 19, the prior art does not disclose “attaching a printed circuit board including a through opening to a first surface of a silicon interposer” and “attaching a semiconductor structure to the first surface of the silicon interposer and within the through opening with a conductive adhesive member” in combination with the remaining claimed features.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899