DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No.11,908,767 in view of Hausenstein (US 2013/0147016.)
Although the claims at issue are not identical, they are not patentably distinct from each other because they disclose the same scope of the invention as a whole. Furthermore, regarding claims 1, 10, and 17, even the cited claims do not mention the redistribution layer over the heat spreader element. However, it is common to one of ordinary skill in the art for such arrangement. For instance, Hausenstein, as disclosed in claims 1, 10, and 17 below, discloses an analogous package and further teaches that the second redistribution layer 151 formed on the hear spreader 40 and 43 to allow more devices to form on top of the dies, thus, reduce the package volume as a whole.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to arrange the elements as taught in order to take the advantage as mentioned above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 10-12, 14-17, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hausenstein (US 2013/0147016.)
In regard to claims 1, 10, and 17, in figs. 15-16 and 21-22, for example, Hausenstein discloses a semiconductor package structure, comprising:
a first redistribution layer, incliding elements 111, 130, 33, 43, for example;
a first semiconductor die DEVICE 1 and a second semiconductor die DEVICE 2 disposed side-by-side over the first redistribution layer;
a thermal spreader 40 and 43 (PARA [0077, fig. 16) vertically overlapping the first semiconductor die and/or the second semiconductor die;
a molding material, or insulation layer, 41 surrounding the thermal spreader, the first semiconductor die and the second semiconductor die; and
a second redistribution layer 151 (para [0100]) disposed over the molding material.
Regarding claim 2, wherein opposite sidewalls of the thermal spreader are substantially aligned with opposite sidewalls of the first semiconductor die. Fig. 16.
Regarding claim 3, wherein opposite sidewalls of the thermal spreader are substantially aligned with a sidewall of the first semiconductor die and a sidewall of the second semiconductor die. Fig. 19.
Regarding claim 11, wherein the thermal spreader has a larger projection area than the first semiconductor die and the second semiconductor die. Fig. 21, for example.
Regarding claims 12 and 14, wherein the thermal spreader is in contact with the second redistribution layer through adhesive 211 (para [0106], and fig. 21.)
Regarding claim 15, wherein the adhesion layer is surrounded by the molding material. Fig. 21.
Regarding claim 16, wherein the adhesion layer is disposed in the second redistribution layer. Fig. 21
Regarding claim 19, wherein the second semiconductor die is bonded onto the second redistribution layer through an adhesion layer. Fig. 21.
Regarding claim 20, wherein the thermal spreader has a larger projection area than the first semiconductor die. Fig. 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hausenstein as applied to claim 1 above, and further in view of JANG (US 2021/0327780.)
Regarding claims 4 and 5, Hausenstein discloses all of the claimed limitations as mentioned above. Hausenstein also discloses a plurality of conductive pillars disposed between the first redistribution layer and the second redistribution layer, except, the plurality of conductive pillars disposed between the first redistribution layer and the second redistribution layer and arranged in a first direction in a top view, wherein the first semiconductor die has a first sidewall and the second semiconductor die has a second sidewall, and the first sidewall and the second sidewall extend in a second direction which is different from the first direction.
Jang, in figs. 1-2, discloses an analogous package 100 including a plurality of conductive pillars 21/22/1b, for example, disposed between the first redistribution layer and the second redistribution layer and arranged in a first direction in a top view, wherein the first semiconductor die has a first sidewall and the second semiconductor die has a second sidewall, and the first sidewall and the second sidewall extend in a second direction which is different from the first direction.
The pillars further provide electrical connections between the layers. This is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to include the pillars as taught in order to provide further electrical connections to external devices.
Regarding claim 6, the cross section shows the spreader covers the sidewalls dies. Figs. 14 and 21.
Regarding claim 7, Hausenstein further shows a third sidewall that is not corded by the spreader. Fig. 21.
Regarding claim 8, the dies are arranged in the same direction. Fig. 21.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hausenstein and Kang as applied to claims 1 and 5 above, and further in view of Eisherbial et al. (US 2022/0199546, hereinafter, Eisherbial.)
Regarding claim 9, Hausenstein discloses all of the claimed limitations as mentioned above, except the dies are arranged in directions opposite to each other, or stacking arrangement.
Eisherbial, in fig. 1, discloses an analogous package including semiconductor devices arranged in a first and second directions opposite to each other in order to facilitate the electrical connections and reduce the package’s surface area. This common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to form the dies in the agreement as taught in order to facilitate the electrical connections and reduce the package’s surface area.
Claim(s) 13 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hausenstein as applied to claims 10 and 17 above, and further in view of KIM et al. (US 2019/0013288, hereinafter, Kim.)
In regard to claims 13 and 18, Hausenstein discloses all of the claimed limitations as mentioned above, except, wherein a thickness of the second semiconductor die is greater than a total thickness of the first semiconductor die and the thermal spreader.
Kim, in fig. 4, discloses an analogous device including a first die 1 and a second die 2 on a first redistribution layer, below the dies and a second redistribution layer above the dies wherein the spreader is embedded and further the die 2 has a thickness greater than die 1 and the heat spreader 420. The arrangement facilitates the steps of insulating the devices and forming other elements on the surface since it is even.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to form the thicknesses as taught in order to take the advantage as mentioned.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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/NATHAN W HA/ Primary Examiner, Art Unit 2814