DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 3-4, 6-8 and 10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Species (B-E and F2-F3), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 31 March 2026.
Applicant’s election without traverse of Species A and Sub-Species F1 in the reply filed on 31 March 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12 January 2024 and 21 January 2025 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "the module" in line 1. There is insufficient antecedent basis for this limitation in the claim. The Examiner will interpret “The module” as “The semiconductor device” for the purpose of examination.
Claim 14 recites the limitation "the module" in line 1. There is insufficient antecedent basis for this limitation in the claim. The Examiner will interpret “The module” as “The semiconductor device” for the purpose of examination.
Claim 15 recites the limitation "the module" in line 1. There is insufficient antecedent basis for this limitation in the claim. The Examiner will interpret “The module” as “The semiconductor device” for the purpose of examination.
Claim 16 recites the limitation "the module" in line 1. There is insufficient antecedent basis for this limitation in the claim. The Examiner will interpret “The module” as “The semiconductor device” for the purpose of examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 9 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Satoshi Shindo et al. (US 2016/0322164 A1; hereinafter “Shindo”).
Regarding Claim 1, Shindo teaches a semiconductor device, comprising:
a substrate (2, Fig. 1, para [0018] describes a substrate 2) having a first main surface (FS, annotated Fig. 1 depicts a first main surface FS of the substrate 2) and a second main surface opposite to each other in a thickness direction (SS, annotated Fig. 1 depicts a second main surface SS of the substrate 2 opposite to the first main surface FS in a thickness direction T);
a circuit layer on the first main surface of the substrate (CL, annotated Fig. 1 depicts a circuit layer CL on the first main surface FS of the substrate 2), wherein the circuit layer has a first electrode layer on a side thereof proximal to the substrate (3a, Fig. 1, para [0020] describes a lower electrode film 3a on a side thereof proximal to the substrate 2), a second electrode layer facing the first electrode layer (3c, Fig. 1, para [0020] describes an upper electrode film 3c facing the first electrode layer 3a), a dielectric layer between the first electrode layer and the second electrode layer in the thickness direction (3b, annotated Fig. 1, para [0020] describes a dielectric film 3b between the first electrode layer 3a and the second electrode layer 3c in a thickness direction T), a first outer electrode extending to a surface of the circuit layer on a side opposite to the substrate (11b, annotated Fig. 1, para [0027] describes an outer electrode 11b extending to a surface of the circuit layer CL on a side opposite to the substrate 2) and a second outer electrode extending to the surface of the circuit layer on the side opposite to the substrate and separated from the first outer electrode (11a, annotated Fig. 1, para [0027] describes a second outer electrode 11a extending to a surface of the circuit layer CL on a side opposite to the substrate 2 and separated from the first outer electrode 11b); and
a first resin body between an end portion of the substrate and the first outer electrode (5b, annotated Fig. 1, para [0023] describes a resin layer 5b between an end portion EP2 of the substrate 2 and the first outer electrode 11b), and between the end portion of the substrate and the second outer electrode in a plan view in the thickness direction (5b, annotated Fig. 1, para [0023] describes a resin layer 5b between an end portion EP1 of the substrate 2 and the second outer electrode 11a wherein a plan view or top down view of annotated Fig. 1 in a thickness direction would put the resin layer 5b between an end portion of the substrate EP1 and the second outer electrode 11a),
in the thickness direction (T, annotated Fig. 1), a leading end of the first resin body on the side opposite to the substrate is positioned higher than top ends of the first outer electrode and the second outer electrode on the side opposite to the substrate (LE, annotated Fig. 1, para [0027] describes wherein first outer electrode 11b and second outer electrode 11a are disposed in cavities 10b and 10a of the first resin body 5b wherein a leading end LE is positioned higher than top ends of the first outer electrode 11b and second outer electrode 11a as shown in annotated Fig 1), and
in a sectional view in a direction perpendicular to the thickness direction (Fig. 1 depicts a sectional view), a first side surface of the first resin body on a side close to the first outer electrode or close to the second outer electrode (FSS, annotated Fig. 1 depicts a first side surface FSS of the first resin body 5b on a side close the first outer electrode 11b) approaches a second side surface of the first resin body on a side close to the end portion of the substrate from the side close to the substrate toward the side opposite to the substrate (SSS, annotated Fig. 1 depicts wherein the first side surface FSS approaches a second side surface SSS on a side close the end portion EP2 of the substrate 2 toward the side opposite to the substrate 2), and the second side surface of the first resin body on the side close to the end portion of the substrate rises steeply against the first main surface of the substrate (SSS, annotated Fig. 1 depicts wherein the second side surface SSS rises steeply against the first main surface FS of the substrate 2 at approximately a 90 degree angle to the first main surface FS).
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Regarding Claim 5, Shindo teaches the semiconductor device according to Claim 1, wherein the first resin body (5b, Fig. 1) has a first outer peripheral portion along the end portion of the substrate and between the end portion of the substrate and the first outer electrode in the plan view in the thickness direction (FPP, annotated Fig. 1 II depicts wherein the first resin body 5b has a first outer peripheral portion FPP along the end portion EP2 of the substrate 2 from annotated Fig. 1, wherein the first outer peripheral portion FPP is between the end portion EP2 and the first outer electrode 11b and further wherein looking at annotated Fig. 1 II from a plan view in the thickness direction T, the first outer peripheral portion FPP would remain along an end portion EP2 of the substrate 2 and between the end portion EP2 and the first outer electrode 11b), and a second outer peripheral portion along the end portion of the substrate and between the end portion of the substrate and the second outer electrode in the plan view in the thickness direction (SPP, annotated Fig. 1 II depicts wherein the first resin body 5b has a second outer peripheral portion SPP along the end portion EP1 of the substrate 2 from annotated Fig. 1, wherein the second outer peripheral portion SPP is between the end portion EP1 and the second outer electrode 11a in annotated Fig. 1 II and further wherein looking at annotated Fig. 1 II from a plan view in the thickness direction T, the second outer peripheral portion SPP would remain along an end portion EP1 of the substrate 2 and between the end portion EP1 and the second outer electrode 11a).
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Regarding Claim 9, Shindo teaches the semiconductor device according to Claim 1,
wherein the first outer electrode is electrically connected to the first electrode layer (11b and 3a, Fig. 1, para [0024] describes a second extended wiring 7b and a third rewiring 8c which electrically connect the first outer electrode 11b and the first electrode layer 3a), and
the second outer electrode is electrically connected to the second electrode layer (11a and 3c, Fig. 1, para [0024] describes a first extended wiring 7a, a first rewiring 8a and a second rewiring 8b which electrically connect the second outer electrode 11a and the second electrode layer 3c).
Regarding Claim 14, Shindo teaches the semiconductor device according to Claim 1, wherein an indentation elastic modulus of the first resin body is lower than an indentation elastic modulus of the dielectric layer (5b and 3b, Fig. 1, para [0020] describes wherein the dielectric film 3b may be comprised of silicon dioxide and para [0023] describes wherein the first resin body 5b may be an epoxy resin or a polyimide resin wherein it is well-known in the art that an epoxy resin or a polyimide resin may have a lower indentation elastic modulus than a dielectric layer comprising silicon dioxide and further wherein the dielectric film 3b of Shindo may comprise a same silicon dioxide as described in the dielectric film of the instant application and wherein the first resin body 5b of Shindo may comprise a same epoxy resin or a polyimide resin such as described in the first resin body of the instant application, please see MPEP 2112.01 (I) wherein the structure of the dielectric layer 3b and first resin body 5b as recited by Shindo is substantially identical to that of the claims therefore claimed properties, such as indentation elastic modulus, or functions are presumed to be present).
Regarding Claim 15, Shindo teaches the semiconductor device according to Claim 1, wherein a Young's modulus of the first resin body is 20 GPa or less (5b, Fig. 1, para [0023] describes wherein the first resin body 5b may be an epoxy resin or a polyimide resin wherein it is well-known in the art that an epoxy resin or a polyimide resin may have a Young’s modulus of 20 GPa or less and further wherein the first resin body 5b of Shindo may comprise a same epoxy resin or a polyimide resin such as described in the first resin body of the instant application, please see MPEP 2112.01 (I) wherein the structure of the first resin body 5b as recited by Shindo is substantially identical to that of the claims therefore claimed properties, such as indentation elastic modulus or Young’s modulus, or functions are presumed to be present).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Satoshi Shindo et al. (US 2016/0322164 A1; hereinafter “Shindo”) in view of Choe Kyong-Gu et al. (JP 2012015299 A using Espacenet English ; hereinafter “Kyong-Gu”).
Regarding Claim 2, Shindo discloses all the limitations of claim 1.
Shindo fails to explicitly disclose the semiconductor device according to claim 1, wherein in the sectional view in the direction perpendicular to the thickness direction, the leading end of the first resin body on the side opposite to the substrate has an acute angle.
However, Kyong-Gu teaches a similar semiconductor device wherein in the sectional view in the direction perpendicular to the thickness direction (TD, annotated Fig. 6 depicts a sectional view of a semiconductor device in a direction perpendicular to a thickness direction TD), the leading end of the first resin body on the side opposite to the substrate has an acute angle (10d and AA, annotated Fig. 6, para [0055] describes wherein upper surfaces of resin projection support portions 10c and 10d are formed to be inclined at an acute angle AA as shown in annotated Fig.6).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Shindo with Kyong-Gu to further disclose a semiconductor device wherein a leading end of the first resin body on the side opposite to the substrate has an acute angle in order to provide the advantage improving mounting reliability of a capacitor and prevents mechanical failure and damage to the underlying dielectric layer (Kyong-Gu, para [0058]).
Regarding Claim 13, Shindo discloses all the limitations of claim 1.
Shindo fails to explicitly disclose the semiconductor device according to claim 1, wherein in the thickness direction, a protruding measurement of the first resin body relative to the circuit layer is 50 μm or less.
However, Kyong-Gu teaches a similar semiconductor device wherein in the thickness direction, a protruding measurement of the first resin body relative to the circuit layer is 50 μm or less (T1, 10a and 10b, Fig. 3 and Fig. 4, para [0041] describes wherein a thickness T1 of resin protrusion supports 10a and 10b are 1 μm to 100 μm from a top surface of a circuit layer which comprises circuit elements 3, 4, 5a, 5b, 6, 7 and 8, wherein a thickness of 25 μm in the range of 1 μm to 100 μm would fall within the range of 50 μm or less).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Shindo with Kyong-Gu to further disclose a semiconductor device wherein a protruding measurement of the first resin body relative to the circuit layer is 50 μm or less in order to provide the well-known advantage of reducing a total thickness of a semiconductor device improving semiconductor device density in electronic component packages leading to improved device performance and higher yield in a manufacturing process.
Regarding Claim 16, Shindo discloses all the limitations of claim 1.
Shindo fails to explicitly disclose the semiconductor device according to claim 1, wherein the first resin body is a cured product of a photosensitive resin.
However, Kyong-Gu teaches a similar semiconductor device wherein the first resin body is a cured product of a photosensitive resin (10a and 10b, Fig. 3 and Fig. 4, para [0041] describes wherein a first resin body comprising support parts 10a and 10b is a negative-type photosensitive polyimide resin and para [0045] describes curing said photosensitive resin).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Shindo with Kyong-Gu to further disclose a semiconductor device wherein a first resin body is a cured product of a photosensitive resin in order to provide the advantage of enabling a resin layer to be formed at specific locations of a semiconductor device so that underlying layers may be protected by the resin layer (Kyong-Gu, para [0043]) and to further perform a process of forming a resin body which ensured adhesion between the resin layer and underlying layers preventing potential undesirable errors in the manufacturing process (Kyong-Gu, para [0042]).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Satoshi Shindo et al. (US 2016/0322164 A1; hereinafter “Shindo”) in view of Chia-Ming Huang et al. (US 2021/0375748 A1; hereinafter “Huang”).
Regarding Claim 11, Shindo discloses all the limitations of claim 1.
Shindo discloses a module, comprising: the semiconductor device according to Claim 1 (1, Fig. 1, para [0017] describes the semiconductor device 1 of claim 1);
Shindo fails to explicitly disclose a wiring substrate having a first land electrically connected to the first outer electrode and a second land electrically connected to the second outer electrode.
However, Huang teaches a similar module (86, Fig. 15, para [0041] describes a package 86), comprising:
a wiring substrate (80, Fig. 15, para [0041] describes a package component 80 that may comprise a package substrate or a printed circuit board) having a first land (83, Fig. 15, para [0041] describes electrical connectors 83) electrically connected to the first outer electrode (83 and 66A, para [0041] describes wherein an electrical connector 83 of the wiring substrate 80 is electrically connected to a first outer electrode 66A) and a second land (83, Fig. 15, para [0041] describes electrical connectors 83) electrically connected to the second outer electrode (83 and 66A, para [0041] describes wherein an electrical connector 83 of the wiring substrate 80 is electrically connected to a second outer electrode 66B).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Shindo with Huang to further disclose a module comprising a wiring substrate having a first land electrically connected to the first outer electrode and a second land electrically connected to the second outer electrode in order to provide the well-known advantage of providing a package component which may include a wiring substrate enabling electrical signals to be routed to and from an underlying semiconductor device capacitor structure increasing device functionality and enabling the semiconductor device to be used in a large scale electronic package.
Regarding Claim 12, the combination of Shindo and Huang discloses the module according to Claim 11, further comprising
a mold resin between the wiring substrate and each of the first outer electrode and the second outer electrode (Huang, 70, Fig. 15, para [0035] describes a planarization layer 70 which may comprise an epoxy/polymer wherein at least a portion of the resin based material planarization layer 70 can be seen between a lower surface of the wiring substrate 80 an upper surface of each of the first outer electrode 66A and the second outer electrode 66B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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