Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements filed on 03/21/2024 and 10/30/2023 have been considered.
Drawings
The drawings filed on 10/30/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 10/30/2023 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 11-19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Jain et al. (US 2018/0269355).
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Regarding claim 1, Jain et al. (US 2018/0269355) discloses:
A substrate (12, ¶0057) comprising:
a first plurality of structures (44b,¶0082) formed on a growth surface (¶0079-¶0082) of the substrate (12), wherein the first plurality of structures (44b) are formed in a multi-periodic pattern, the multi-periodic pattern including a first plurality of groups of structures (44b), wherein each group of structures has a first characteristic spacing between adjacent structures in the group of structures, and wherein each group of structures is separated from an adjacent group of structures by a second characteristic spacing, wherein the second characteristic spacing is at least 1.5 times larger than the first characteristic spacing (figure 18).
Regarding claim 2, Jain further discloses:
wherein each group of structures comprises a hexagonal arrangement of structures (¶0058).
Regarding claim 3, Jain further discloses:
wherein each group of structures includes a plurality of sides, wherein two sides of the plurality of sides of each group are aligned perpendicular to or in parallel with an A-plane of the substrate.
Regarding claim 4, Jain further discloses:
a second plurality of structures (44a) formed on the growth surface of the substrate, wherein the second plurality of structures are formed in a second multi-periodic pattern (¶0079, ¶0082) .
Regarding claim 5, Jain further discloses;
wherein the first multi-periodic pattern (44b) is embedded within the second multi-periodic pattern (44a, figure 18).
Regarding claim 65, Jain further discloses:
wherein the second plurality of structures (44a) have a characteristic lateral size at least 1.5 times larger than a characteristic lateral size of the first plurality of structures (44b, figure 18).
Regarding claim 7, Jain further discloses:
wherein each structure (44b) has a lateral size similar to the first characteristic spacing (¶0057).
Regarding claims 8 and 15, Jain discloses:
A semiconductor device comprising:
a substrate (12) including a first plurality of structures formed on a growth surface of the substrate, wherein the first plurality of structures are formed in a multi-periodic pattern, the multi-periodic pattern including a first plurality of groups (44b) of structures, wherein each group of structures has a first characteristic spacing between adjacent structures in the group of structures, and wherein each group of structures is separated from an adjacent group of structures by a second characteristic spacing, wherein the second characteristic spacing is at least 1.5 times larger than the first characteristic spacing (¶0079-0082); and
a semiconductor layer (74, ¶0064) grown directly on the substrate (12).
Regarding claim 9, Jain further discloses:
wherein each group of structures comprises a hexagonal arrangement of structures (¶0058).
Regarding claim 11, Jain further discloses:
a second plurality of structures (44a) formed on the growth surface of the substrate (12), wherein the second plurality of structures are formed in a second multi-periodic pattern (figure 18).
Regarding claim 12, Jain further discloses:
wherein the semiconductor layer (74) has a thickness sufficient for the semiconductor material to coalesce above a spacing between adjacent groups of structures (figure 10, ¶0064).
Regarding claim 13, Jain further discloses:
wherein the semiconductor layer comprises a buffer layer (14, ¶0043), the semiconductor device further including a plurality of active layers (18, ¶0043) grown on the semiconductor layer (12).
Regarding claim 14, Jain further discloses:
wherein the active layers are configured to operate as an optoelectronic device (¶0043).
Regarding claim 16, Jain further discloses:
wherein the forming the first plurality of structures includes etching the substrate (¶0059).
Regarding claim 17,m Jain further discloses:
wherein the growing causes the semiconductor layer to coalesce into a substantially contiguous layer (¶0061).
Regarding claim 18, Jain further discloses:
growing a plurality of active layers (18) on the semiconductor layer (figure 18).
Regarding claim 19, Jian further discloses:
wherein each group of structures comprises a hexagonal arrangement of structures (¶0058).
Allowable Subject Matter
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 10 and 20, the prior art does not disclose “wherein each group of structures includes a plurality of sides, wherein two sides of the plurality of sides of each group are aligned perpendicular to or in parallel with an A-plane of the substrate.” In combination with the remaining claimed features.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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/WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899