DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 10 is objected to because of the following informalities: Claim 10 recites “a gate structure in direct contact against the fist (emphasis added) . . .” This is believed to be a typo and that “fist” should be changed to “first.” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "the second S/D contact" in lines 3 and 4 of the claim. There is insufficient antecedent basis for this limitation in the claim. The structure of “a second backside contact in direct contact against the second S/D region” is claimed in claim 12 on which claim 13 depends and it is believed that the feature “the second S/D contact” is meant to be the “second backside contact” and the claims are being examined based on that interpretation. Claims 14-17 depend from this claim and therefore inherit its deficiency. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 9-14, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20220336287 (Yu et al).
Concerning claim 1, Yu discloses a semiconductor integrated circuit (IC) device comprising (Figs. 8(A1)- 8(C4)): a transistor comprising a plurality of nanosheet channels (154) ([0021]); a bottom isolation structure (140) below the plurality of nanosheet channels (Fig. 8(C1)); a bottom isolation extension (BIE) region (121) in direct contact against at least a sidewall of the bottom isolation structure (Fig. 8(C1)); and a gate structure (112) in direct contact against the BIE region and in direct contact against the plurality of nanosheet channels (Fig. 8(C1)).
Considering claim 10, Yu discloses a semiconductor integrated circuit (IC) device comprising (Figs. 8(A1)- 8(C4)): a first transistor associated with a first active region (106) ([0021], note that there are several active regions shown and each of the transistors that are formed over the active regions comprise the same structures), the first transistor comprising a first plurality of nanosheet channels (154) (Fig. 8(A1)), a first bottom isolation structure (140) below the first plurality of nanosheet channels (Fig. 8(C1)), and a first bottom isolation extension (BIE) region (121) in direct contact against at least a sidewall of the first bottom isolation structure (Fig. 8(C1)); a second transistor associated with a second active region (106) ([0021], note that there are several active regions shown and each of the transistors that are formed over the active regions comprise the same structures), the second transistor comprising a second plurality of nanosheet channels (154), a second bottom isolation structure (140) below the second plurality of nanosheet channels (Fig. 8(C1)), and a second BIE region (121) in direct contact against at least a sidewall of the second bottom isolation structure (Fig. 8(C1)); a shallow trench isolation (STI) region (104) between the first active region and the second active region (Fig. 8(C1)); and a gate structure (112) in direct contact against the fist BIE region (Fig. 8(C1)), in direct contact against the first plurality of nanosheet channels, in direct contact against the second BIE region, in direct contact against the second plurality of nanosheet channels, and in direct contact against the STI region (Fig. 8(C1)).
Continuing to claims 2, 11, and 12 , Yu discloses further comprising: a source/drain (S/D) region (108) in direct contact against the plurality of nanosheet channels (Fig. 8A(6)); and a backside contact (120) in direct contact against the S/D region (Fig. 8 (B6)), wherein the first transistor further comprises a first source/drain (S/D) region (108) in direct contact against the first plurality of nanosheet channels (Fig. 8A(6)); and wherein the second transistor further comprises a second S/D region in direct contact against the second plurality of nanosheet channels (Fig. 8A(6) and [0021], note that each of the transistors that are formed over the active regions comprise the same structures), and further comprising: a first backside contact (120) in direct contact against the first S/D region (Fig. 8(B6)); and a second backside contact in direct contact against the second S/D region (Fig. 8B(6) and [0021], note that each of the transistors that are formed over the active regions comprise the same structures).
Referring to claim 3, Yu discloses wherein the BIE region is further in direct contact against the backside contact (Fig. 8(B6)).
Regarding claim 4, Yu discloses further comprising: a backside back end of line (BEOL) network (118) in direct contact against the backside contact ([0064]).
Pertaining to claim 5, Yu discloses further comprising: a shallow trench isolation (STI) region (104) underneath the gate structure (Fig. 8(C1)).
As to claims 9 and 18, Yu discloses wherein the BIE region is composed of a first material ([0032], note that a material of the BIE region is disclosed to be SiON and the examiner is relying on this for rejection purposes), wherein the bottom isolation structure is composed of a second material ([0019], note that the material of the bottom isolation structure is disclosed to be chosen based on etch selectivites with a disclosed material being SiO which the examiner is relying on for rejection purposes), and wherein the first material is different than the second material and wherein the first BIE region and the second BIE region are composed of a first material ([0032], note that a material of the BIE region is disclosed to be SiON and the examiner is relying on this for rejection purposes), wherein the first bottom isolation structure composed of a second material ([0019], note that the material of the bottom isolation structure is disclosed to be chosen based on etch selectivites with a disclosed material being SiO which the examiner is relying on for rejection purposes), and wherein the first material is different than the second material.
Concerning claim 13, Yu discloses further comprising a backside interlayer dielectric (ILD) (134), wherein the first BIE region is further in direct contact against the first backside contact, and wherein the backside ILD is between the second BIE region and the second S/D contact ([0101] and Fig. 8(A6)).
Considering claim 14, Yu discloses further comprising: a backside back end of line (BEOL) network (118) in direct contact against the first backside contact and in direct contact against the second S/D contact ([0064]).
Continuing to claim 19, Yu discloses a semiconductor integrated circuit (IC) device fabrication method comprising (Figs. 5(A1)- 5(C4)): forming a gate structure (112) upon and around channels (154) and upon a bottom isolation structure (140) of a first transistor ([0021]); forming a bottom isolation extension (BIE) region opening within the gate structure, the BIE region opening exposing at least a sidewall of the bottom isolation structure (Fig. 5(A2)); and forming a BIE region (121) by depositing dielectric material within the BIE region opening ([0032] and Fig. 5(A4)).
Referring to claim 20, Yu discloses wherein the BIE region is in direct contact against the sidewall of the bottom isolation structure (Fig. 5(A3)) and is indirect contact with the gate structure (Fig. 5(C3)).
Allowable Subject Matter
Claims 6-8 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 6 recites the limitations wherein a bottom surface of the BIE region is substantially coplanar with a bottom surface of the gate structure. This closest prior art reference US 20220336287 does not teach not suggest this limitation (as seen in Fig. 1 of the present application) in combination with the other limitations as set forth in the claims. Claims 7 and 8 depend from this claim and contain allowable subject matter for that reason.
Claim 15 recites the limitations wherein a bottom surface of the first BIE region, a bottom surface of the second BIE region, and a bottom surface of the gate structure are substantially coplanar. This closest prior art reference US 20220336287 does not teach not suggest this limitation (as seen in Fig. 1 of the present application) in combination with the other limitations as set forth in the claims. Claims 16 and 17 depend from this claim and contain allowable subject matter for that reason.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20210336012 discloses a semiconductor device that includes a bottom isolation structure and a bottom isolation extension region formed on the sidewalls of the bottom isolation structure (Fig. 15B).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/Examiner, Art Unit 2897 01/14/26
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897