DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 and 14-22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yoshimura et al. (US 2023/0420446) (hereafter Yoshimura).
Regarding claim 1, Yoshimura discloses a semiconductor device, comprising:
a first power supply pad 8 (Fig. 9, paragraph 0036) configured to receive a first power supply voltage (“5 V” in paragraph 0034);
a second power supply pad 9 (Fig. 9, paragraph 0036) configured to receive a second power supply voltage (“reference voltage” in paragraph 0034), the second power supply voltage (“reference voltage” in paragraph 0034) having a level lower than a level of the first power supply voltage (“5 V” in paragraph 0034);
a signal pad 7 (Fig. 9, paragraph 0094) configured to exchange a signal (see paragraph 0094, wherein “A signal input into the input-output pad 7 is input into the internal circuit 3 through the input-output wiring line 2”); and
a first electrostatic discharge (ESD) diode 4A (Fig. 9, paragraph 0095) comprising a first impurity region 30A (Fig. 9, paragraph 0103) doped with impurities of a first conductivity type (“n” in Fig. 9) and connected to the first power supply pad 8 (Fig. 9), and a second impurity region 40A (Fig. 9, paragraph 0103) doped with impurities of a second conductivity type (“p” in Fig. 9) different from the first conductivity type (“n” in Fig. 9) and connected to the signal pad 7 (Fig. 9), wherein a lower surface of at least one of the first impurity region 30A (Fig. 10A) and the second impurity region 40A (Fig. 10A) has an uneven structure (see Fig. 10A and paragraph 0055, wherein “The first bottom wall portion 32A includes a curved portion that protrudes to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the curved portions together.”; and see paragraph 0062, wherein “The first bottom wall 43A includes an outer curved portion and an inner curved portion both of which protrude to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the outer curved portion and the inner curved portion together”).
Regarding claim 2, Yoshimura further discloses the semiconductor device of claim 1, wherein the first impurity region 30A (Fig. 9) and the second impurity region 40A (Fig. 9) are disposed in a first well region 20A (Fig. 10A, paragraph 0097) formed on a substrate 10 (Fig. 10A, paragraph 0073), and the first well region 20A (Fig. 10A) is doped with impurities of the first conductivity type (“n-“ in Fig. 10A).
Regarding claim 3, Yoshimura further discloses the semiconductor device of claim 2, wherein a doping concentration of the first impurity region 30A (Fig. 9, paragraph 0054, wherein “not less than 10×10.sup.17 cm.sup.−3 and not more than 10×10.sup.20 cm.sup.−3”) is greater than a doping concentration of the first well region 20A (Fig. 10A, paragraph 0052, wherein “not less than 1.0×10.sup.15 cm.sup.−3 and not more than 1.0×10.sup.18 cm.sup.−3”).
Regarding claim 4, Yoshimura further discloses the semiconductor device of claim 2, wherein the first well region 20A (Fig. 10A, paragraph 0097) is a deep N-well region (“n-“ in Fig. 10A).
Regarding claim 5, Yoshimura further discloses the semiconductor device of claim 2, wherein at least some region of a side surface of the first impurity region 30A (Fig. 10A) contacting the first well region 20A (Fig. 10A) has an uneven structure (see Fig. 10A and paragraph 0055, wherein “The first bottom wall portion 32A includes a curved portion that protrudes to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the curved portions together.” such that lower side surface of 30A is curved in Fig. 10A).
Regarding claim 6, Yoshimura further discloses the semiconductor device of claim 1, wherein the second impurity region 40A (Fig. 10A) is surrounded by the first impurity region 30A (Fig. 10A) in a plane parallel to an upper surface of a substrate 10 (Fig. 10A), and an element isolation layer 35A (Fig. 10A, paragraph 0058) is disposed between the first impurity region 30A (Fig. 10A) and the second impurity region 40A (Fig. 10A) in the plane parallel to the upper surface of the substrate 10 (Fig. 10A).
Regarding claim 7, Yoshimura further discloses the semiconductor device of claim 6, wherein, in a direction (vertical direction in Fig. 10A) perpendicular to the substrate 10 (Fig. 10A), a depth of the element isolation layer 35A (Fig. 10A) is greater than a maximum depth of the first impurity region 30A (Fig. 10A) and a maximum depth of the second impurity region 40A (Fig. 10A).
Regarding claim 8, Yoshimura (utilized different elements for a first impurity region and a second impurity region as applied in claim 1 in the above) discloses a semiconductor device, comprising:
a first power supply pad 8 (Fig. 9, paragraph 0036) configured to receive a first power supply voltage (“5 V” in paragraph 0034);
a second power supply pad 9 (Fig. 9, paragraph 0036) configured to receive a second power supply voltage (“reference voltage” in paragraph 0034), the second power supply voltage (“reference voltage” in paragraph 0034) having a level lower than a level of the first power supply voltage (“5 V” in paragraph 0034);
a signal pad 7 (Fig. 9, paragraph 0094) configured to exchange a signal (see paragraph 0094, wherein “A signal input into the input-output pad 7 is input into the internal circuit 3 through the input-output wiring line 2”);
a first electrostatic discharge (ESD) diode 4A (Fig. 9, paragraph 0095) comprising a first impurity region 40A (Fig. 9, paragraph 0103) doped with impurities of a first conductivity type (“p” in Fig. 9) and connected to the first power supply pad 8 (Fig. 9), and a second impurity region (20A and 30A in Fig. 9, paragraph 0103) doped with impurities of a second conductivity type (“n” and “n-“ in Fig. 9) different from the first conductivity type (“p” in Fig. 9) and connected to the signal pad 7 (Fig. 9), wherein a lower surface of at least one of the first impurity region 40A (Fig. 10A) and the second impurity region has an uneven structure (see Fig. 10A and paragraph 0062, wherein “The first bottom wall 43A includes an outer curved portion and an inner curved portion both of which protrude to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the outer curved portion and the inner curved portion together”); and
wherein the second impurity region 40A (Fig. 10A) is surrounded by the first impurity region (20A and 30A in Fig. 10A) in a plane parallel to a substrate 10 (Fig. 10A), and at least some region of a side surface of the first impurity region 40A (Fig. 10A) contacting the second impurity region (20A and 30A in Fig. 10A) has an uneven structure (see paragraph 0062, wherein “The first bottom wall 43A includes an outer curved portion and an inner curved portion both of which protrude to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the outer curved portion and the inner curved portion together”).
Regarding claim 9, Yoshimura further discloses the semiconductor device of claim 1, wherein a plurality of first metal wirings 67A (Fig. 4, paragraph 0043) extending in a first direction (horizontal direction in Fig. 4) in a plane parallel to an upper surface of a substrate 10 (Fig. 4), disposed on an upper surface of the first impurity region 30A (Fig. 4), and electrically connected to the first impurity region 30A (Fig. 4); and at least one second metal wiring 72A (Fig. 4, paragraph 0043) extending in the first direction (horizontal direction in Fig. 4), disposed on an upper surface of the second impurity region 40A (Fig. 4), and electrically connected to the second impurity region 40A (Fig. 4).
Regarding claim 10, Yoshimura further discloses the semiconductor device of claim 9, wherein the quantity of the first metal wirings 67A (Fig. 4) is greater than a quantity of the second metal wirings 72A (Fig. 4).
Regarding claim 14, Yoshimura further discloses the semiconductor device of claim 1, further comprising: a second ESD diode 4B (Fig. 9, paragraph 0039) comprising a third impurity region doped 40B (Fig. 9, paragraph 0074) with impurities of the first conductivity type (“n” in Fig. 9) and connected to the signal pad 7 (Fig. 9), and a fourth impurity region 30B (Fig. 9, paragraph 0074) doped with impurities of the second conductivity type (“p” in Fig. 9) and connected to the second power supply pad 7 (Fig. 9).
Regarding claim 15, Yoshimura further discloses the semiconductor device of claim 14, wherein a lower surface of the third impurity region 40B (Fig. 11A) has an uneven structure (see Fig. 11A and paragraph 0083, wherein “The second bottom wall 43B includes an outer curved portion and an inner curved portion both of which protrude to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the outer curved portion and the inner curved portion together.”).
Regarding claim 16, Yoshimura further discloses the semiconductor device of claim 14, wherein the third impurity region 40B (Fig. 9) and the fourth impurity region 30B (Fig. 9) are disposed in a second well region 20B (Fig. 11A, paragraph 0073) formed on a substrate 10 (Fig. 11A, paragraph 0073), and the second well region 20B (Fig. 11A) is doped with impurities of the second conductivity type (“p-“ in Fig. 11A).
Regarding claim 17, Yoshimura discloses a semiconductor device, comprising:
a first ESD diode 4A (Fig. 9, paragraph 0095) connected between a first power supply pad 8 (Fig. 9, paragraph 0036) configured to receive a first power supply voltage (“5 V” in paragraph 0034) and a signal pad 7 (Fig. 9, paragraph 0094); and
a second ESD diode 4B (Fig. 9, paragraph 0095) connected between a second power supply pad 9 (Fig. 9, paragraph 0036) configured to receive a second power supply voltage (“reference voltage” in paragraph 0034) and the signal pad 7 (Fig. 9), the second power supply voltage (“reference voltage” in paragraph 0034) having a level lower than a level of the first power supply voltage (“5 V” in paragraph 0034),
wherein the first ESD diode 4A (Fig. 9) comprises a first impurity region 30A (Fig. 9, paragraph 0103) doped with N-type impurities (“n” in Fig. 9) and a second impurity region 40A (Fig. 9, paragraph 0103) doped with P-type impurities (“p” in Fig. 9), the second ESD diode 4B (Fig. 9) comprises a third impurity region 40B (Fig. 9, paragraph 0114) doped with N-type impurities (“n” in Fig. 9) and a fourth impurity region 30B (Fig. 9, paragraph 0114) doped with P-type impurities (“p” in Fig. 9), and the first to fourth impurity regions (30A, 40A, 40B, and 30B in Fig. 9) are formed in a well region (20A (Fig. 10A) and 20B (Fig. 11A), paragraphs 0103 and 0114) of a substrate 10 (Figs. 10A and 11A, paragraph 0083), and a lower surface of each of the first impurity region 30A (Fig. 10A) and the third impurity region 40B (Fig. 11A) has an uneven structure (see Fig. 10A and paragraph 0055, wherein “The first bottom wall portion 32A includes a curved portion that protrudes to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the curved portions together.”; and see Fig. 11A and paragraph 0083, wherein “The second bottom wall 43B includes an outer curved portion and an inner curved portion both of which protrude to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the outer curved portion and the inner curved portion together.”).
Regarding claim 18, Yoshimura further discloses the semiconductor device of claim 17, wherein a lower surface of the second impurity region 40A (Fig. 10A) has an uneven structure (see Fig. 10A and paragraph 0062, wherein “The first bottom wall 43A includes an outer curved portion and an inner curved portion both of which protrude to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the outer curved portion and the inner curved portion together”).
Regarding claim 19, Yoshimura further discloses the semiconductor device of claim 17, wherein a lower surface of the fourth impurity region 30B (Fig. 11A, paragraph 0114) has a structure (see paragraph 0075, wherein thickness of 30B is 180 nm; paragraph 0054, wherein thickness of 30A is 140 nm; and paragraph 0078, wherein thickness of 40B is 140 nm) different from a structure of each of the first impurity region 30A (Fig. 10A, paragraph 0103) and the third impurity region 40B (Fig. 11A).
Regarding claim 20, Yoshimura further discloses the semiconductor device of claim 17, wherein the first impurity region 30A (Fig. 10A) and the second impurity region 40A (Fig. 10A) are formed in a first well region 20A (Fig. 10A, paragraph 0103) doped with N-type impurities (“n-“ in Fig. 10A) on the substrate 10 (Fig. 10A), and the third impurity region 40B (Fig. 11A) and the fourth impurity region 30B (Fig. 11A) are formed in a second well region 20B (Fig. 11A, paragraph 0114) doped with P-type impurities (“p-“ in Fig. 11A) on the substrate 10 (Fig. 11A)
Regarding claim 21, Yoshimura discloses a semiconductor device, comprising:
a cell region 1 (Fig. 9, paragraph 0094) in which a plurality of memory cells 3 (Fig. 1, paragraph 0033; and see paragraph 0131, wherein “the present invention can be applied to various electric apparatuses, i.e., can be applied to mobile telecommunications products, such as a mobile phone and PHS (Personal Handyphone System), and pieces of information processing equipment typified by personal computers”) are disposed (see paragraph 0033, wherein “cubic shape”) in a first direction (horizontal direction in Fig. 10A), second direction (stacking direction in Fig. 10A) and a third direction (vertical direction in Fig. 10A), wherein the first (horizontal direction in Fig. 10A) and second directions (stacking direction in Fig. 10A) are parallel to an upper surface of a substrate 10 (Fig. 10A) and intersect each other, and the third direction (vertical direction in Fig. 10A) is perpendicular to the upper surface of the substrate 10 (Fig. 10A);
a peripheral circuit region (4A and 4B in Fig. 9, paragraph 0039) in which peripheral circuits configured to control (see paragraph 0033, wherein “The protection element 4 is an element, chiefly, used to protect the internal circuit 3 from ESD that is input into the input-output wiring line 2”) the plurality of memory cells 3 (Fig. 9) are disposed; and
a plurality of pads (7, 8, and 9 in Fig. 9, paragraph 0036) connected to the peripheral circuits, wherein the peripheral circuit region (4A and 4B in Fig. 9) comprises an ESD diode 4A (Fig. 9, paragraph 0095) connected to at least one signal pad 7 (Fig. 9, paragraph 0094) among the plurality of pads (7, 8, and 9 in Fig. 9), the signal pad 7 (Fig. 9) being configured to exchange a signal (see paragraph 0094, wherein “A signal input into the input-output pad 7 is input into the internal circuit 3 through the input-output wiring line 2”) with external device, the ESD diode 4A (Fig. 9) comprises a first impurity region 30A (Fig. 9, paragraph 0103) doped with N-type impurities (“n” in Fig. 9) and a second impurity region 40A (Fig. 9, paragraph 0103) doped with P-type impurities (“p” in Fig. 9), at least one of the first impurity region 30A (Fig. 10A) and the second impurity region 40A (Fig. 10A) comprises a plurality of first regions 40A (Fig. 10A) having a first thickness (see paragraph 0057, wherein “180 nm) in the third direction (vertical direction in Fig. 10A), and a plurality of second regions 30A (Fig. 10A) having a second thickness (see paragraph 0054, wherein “140 nm) in the third direction (vertical direction in Fig. 10A) less than the first thickness (see paragraph 0057, wherein “180 nm), and the plurality of first regions 40A (Fig. 10A) and the plurality of second regions 30A (Fig. 10A) are disposed to alternate between a first region 40A (Fig. 10A) and a second region 30A (Fig. 10A) in at least one of the first direction (horizontal direction in Fig. 10A) and the second direction.
Regarding claim 22, Yoshimura further discloses the semiconductor device of claim 21, wherein the plurality of pads (8 and 9 in Fig. 9, paragraph 0036) comprises a power supply pad 8 (Fig. 9) configured to receive a power supply voltage (“5 V” in paragraph 0034), and the ESD diode 4A (Fig. 9, paragraph 0095) is connected between the signal pad 7 (Fig. 9) and the power supply pad 8 (Fig. 9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshimura as applied to claim 9 above, and further in view of Yoo et al. (US 2016/0064375) (hereafter Yoo).
Regarding claim 11, Yoshimura discloses the semiconductor device of claim 9, however Yoshimura does not disclose, in a second direction in a plane parallel to the upper surface of the substrate and intersecting the first direction, the second metal wiring is disposed between the first metal wirings.
Yoo disclose, in a second direction (vertical direction in Fig. 8) in a plane parallel to the upper surface of the substrate 21 (Fig. 2, paragraph 0097) and intersecting the first direction (horizontal direction in Fig. 8), the second metal wiring 45 (Fig. 8, paragraph 0046) is disposed between (see Fig. 8, wherein second row of 45 is vertically between first row of 41 and third row of 41) the first metal wirings 41 (Fig. 8, paragraph 0046).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yoshimura to form, in a second direction in a plane parallel to the upper surface of the substrate and intersecting the first direction, the second metal wiring is disposed between the first metal wirings, as taught by Yoo, since outside surfaces of the second impurity region 33 (Yoo, Fig. 8, paragraph 0071), the isolation layer 29 (Yoo, Fig. 8, paragraph 0071), and the high-resistance region 37 (Yoo, Fig. 8, paragraph 0071) each may have a regular hexagonal shape such that the well 25 (Yoo, Fig. 8, paragraph 0071), the third impurity region 35 (Yoo, Fig. 8, paragraph 0071), the second impurity region 33 (Yoo, Fig. 8, paragraph 0071), the isolation layer 29 (Yoo, Fig. 8, paragraph 0071), the high-resistance region 37 (Yoo, Fig. 8, paragraph 0071), and the first impurity region 31 (Yoo, Fig. 8, paragraph 0071) may be configured as an ESD protection device.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813