DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 5/28/2026 is acknowledged.
Applicant amended claims 1, 5, 8, 15, 17, 18, 20, and 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimura et al. (US 2023/0420446) (hereafter Yoshimura), in view of Park et al. (US 2009/0020844) (hereafter Park).
Regarding claim 21, Yoshimura discloses a semiconductor device, comprising:
a cell region 1 (Fig. 9, paragraph 0094) in which a plurality of memory cells 3 (Fig. 1, paragraph 0033; and see paragraph 0131, wherein “the present invention can be applied to various electric apparatuses, i.e., can be applied to mobile telecommunications products, such as a mobile phone and PHS (Personal Handyphone System), and pieces of information processing equipment typified by personal computers”) are disposed (see paragraph 0033, wherein “cubic shape”) in a first direction (horizontal direction in Fig. 10A), second direction (stacking direction in Fig. 10A) and a third direction (vertical direction in Fig. 10A), wherein the first (horizontal direction in Fig. 10A) and second directions (stacking direction in Fig. 10A) are parallel to an upper surface of a substrate 10 (Fig. 10A) and intersect each other, and the third direction (vertical direction in Fig. 10A) is perpendicular to the upper surface of the substrate 10 (Fig. 10A);
a peripheral circuit region (4A and 4B in Fig. 9, paragraph 0039) in which peripheral circuits configured to control (see paragraph 0033, wherein “The protection element 4 is an element, chiefly, used to protect the internal circuit 3 from ESD that is input into the input-output wiring line 2”) the plurality of memory cells 3 (Fig. 9) are disposed; and
a plurality of pads (7, 8, and 9 in Fig. 9, paragraph 0036) connected to the peripheral circuits, wherein the peripheral circuit region (4A and 4B in Fig. 9) comprises an ESD diode 4A (Fig. 9, paragraph 0095) connected to at least one signal pad 7 (Fig. 9, paragraph 0094) among the plurality of pads (7, 8, and 9 in Fig. 9), the signal pad 7 (Fig. 9) being configured to exchange a signal (see paragraph 0094, wherein “A signal input into the input-output pad 7 is input into the internal circuit 3 through the input-output wiring line 2”) with external device, the ESD diode 4A (Fig. 9) comprises a first impurity region 30A (Fig. 9, paragraph 0103) doped with N-type impurities (“n” in Fig. 9) and a second impurity region 40A (Fig. 9, paragraph 0103) doped with P-type impurities (“p” in Fig. 9), at least one of the first impurity region 30A (Fig. 10A) and the second impurity region 40A (Fig. 10A) comprises a plurality of first regions 40A (Fig. 10A) having a first thickness (see paragraph 0057, wherein “180 nm) in the third direction (vertical direction in Fig. 10A), and a plurality of second regions 30A (Fig. 10A) having a second thickness (see paragraph 0054, wherein “140 nm) in the third direction (vertical direction in Fig. 10A) less than the first thickness (see paragraph 0057, wherein “180 nm), and the plurality of first regions 40A (Fig. 10A) and the plurality of second regions 30A (Fig. 10A) are disposed to alternate between a first region 40A (Fig. 10A) and a second region 30A (Fig. 10A) in at least one of the first direction (horizontal direction in Fig. 10A) and the second direction.
Yoshimura does not disclose the plurality of second regions correspond to projections extending vertically upward into the at least one of the first impurity region and the second impurity region.
Park discloses the plurality of second regions 220a (Fig. 4B, paragraph 0071) correspond to projections (region between 220a in Fig. 4B) extending vertically upward into the at least one of the first impurity region (250a and 250b in Fig. 4B) and the second impurity region 220a (Fig. 4B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Yoshimura to form the plurality of second regions correspond to projections extending vertically upward into the at least one of the first impurity region and the second impurity region, as taught by Park, since the second conductive type region 220a (Park, Fig. 4B, paragraph 0071) is formed to surround the first conductive type region 210a (Park, Fig. 4B, paragraph 0071) in a depth direction of the semiconductor substrate 200 (Park, Fig. 4B, paragraph 0071), a guard ring of the schottky diode 51 (Park, Fig. 4B, paragraph 0071) may be formed.
Regarding claim 22, Yoshimura further discloses the semiconductor device of claim 21, wherein the plurality of pads (8 and 9 in Fig. 9, paragraph 0036) comprises a power supply pad 8 (Fig. 9) configured to receive a power supply voltage (“5 V” in paragraph 0034), and the ESD diode 4A (Fig. 9, paragraph 0095) is connected between the signal pad 7 (Fig. 9) and the power supply pad 8 (Fig. 9).
Allowable Subject Matter
Claims 1-11 and 14-20 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Yoshimura et al. (US 2023/0420446), discloses a first electrostatic discharge (ESD) diode 4A (Fig. 9, paragraph 0095) comprising a first impurity region 30A (Fig. 9, paragraph 0103) doped with impurities of a first conductivity type (“n” in Fig. 9) and connected to the first power supply pad 8 (Fig. 9), and a second impurity region 40A (Fig. 9, paragraph 0103) doped with impurities of a second conductivity type (“p” in Fig. 9) different from the first conductivity type (“n” in Fig. 9) and connected to the signal pad 7 (Fig. 9), wherein a lower surface of at least one of the first impurity region 30A (Fig. 10A) and the second impurity region 40A (Fig. 10A) has an uneven structure (see Fig. 10A and paragraph 0055, wherein “The first bottom wall portion 32A includes a curved portion that protrudes to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the curved portions together.”; and see paragraph 0062, wherein “The first bottom wall 43A includes an outer curved portion and an inner curved portion both of which protrude to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the outer curved portion and the inner curved portion together”) but fails to disclose an uneven structure comprising projections extending vertically upward into the impurity region from the lower surface. Additionally, the prior art does not teach or suggest a semiconductor device, comprising: an uneven structure comprising projections extending vertically upward into the impurity region from the lower surface in combination with other elements of claim 1.
In addition, a closest prior art, Yoshimura et al. (US 2023/0420446), discloses the first ESD diode 4A (Fig. 9) comprises a first impurity region 30A (Fig. 9, paragraph 0103) doped with N-type impurities (“n” in Fig. 9) and a second impurity region 40A (Fig. 9, paragraph 0103) doped with P-type impurities (“p” in Fig. 9), the second ESD diode 4B (Fig. 9) comprises a third impurity region 40B (Fig. 9, paragraph 0114) doped with N-type impurities (“n” in Fig. 9) and a fourth impurity region 30B (Fig. 9, paragraph 0114) doped with P-type impurities (“p” in Fig. 9), and the first to fourth impurity regions (30A, 40A, 40B, and 30B in Fig. 9) are formed in a well region (20A (Fig. 10A) and 20B (Fig. 11A), paragraphs 0103 and 0114) of a substrate 10 (Figs. 10A and 11A, paragraph 0083), and a lower surface of each of the first impurity region 30A (Fig. 10A) and the third impurity region 40B (Fig. 11A) has an uneven structure (see Fig. 10A and paragraph 0055, wherein “The first bottom wall portion 32A includes a curved portion that protrudes to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the curved portions together.”; and see Fig. 11A and paragraph 0083, wherein “The second bottom wall 43B includes an outer curved portion and an inner curved portion both of which protrude to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the outer curved portion and the inner curved portion together.”) but fails to disclose an uneven structure comprising projections with a first group of the projections extending vertically into the first impurity region from the lower surface of the first impurity region and a second group of the projections extending vertically into the third impurity region from a lowest extent of the lower surface of the third impurity region. Additionally, the prior art does not teach or suggest a semiconductor device, comprising: an uneven structure comprising projections with a first group of the projections extending vertically into the first impurity region from the lower surface of the first impurity region and a second group of the projections extending vertically into the third impurity region from a lowest extent of the lower surface of the third impurity region in combination with other elements of claim 17.
A closest prior art, Yoshimura et al. (US 2023/0420446), discloses a semiconductor device, comprising: a first power supply pad 8 (Fig. 9, paragraph 0036) configured to receive a first power supply voltage (“5 V” in paragraph 0034); a second power supply pad 9 (Fig. 9, paragraph 0036) configured to receive a second power supply voltage (“reference voltage” in paragraph 0034), the second power supply voltage (“reference voltage” in paragraph 0034) having a level lower than a level of the first power supply voltage (“5 V” in paragraph 0034); a signal pad 7 (Fig. 9, paragraph 0094) configured to exchange a signal (see paragraph 0094, wherein “A signal input into the input-output pad 7 is input into the internal circuit 3 through the input-output wiring line 2”); and a first electrostatic discharge (ESD) diode 4A (Fig. 9, paragraph 0095) comprising a first impurity region 30A (Fig. 9, paragraph 0103) doped with impurities of a first conductivity type (“n” in Fig. 9) and connected to the first power supply pad 8 (Fig. 9), and a second impurity region 40A (Fig. 9, paragraph 0103) doped with impurities of a second conductivity type (“p” in Fig. 9) different from the first conductivity type (“n” in Fig. 9) and connected to the signal pad 7 (Fig. 9), wherein a lower surface of at least one of the first impurity region 30A (Fig. 10A) and the second impurity region 40A (Fig. 10A) has an uneven structure (see Fig. 10A and paragraph 0055, wherein “The first bottom wall portion 32A includes a curved portion that protrudes to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the curved portions together.”; and see paragraph 0062, wherein “The first bottom wall 43A includes an outer curved portion and an inner curved portion both of which protrude to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the outer curved portion and the inner curved portion together”) but fails to teach an uneven structure comprising projections extending vertically upward into the impurity region from the lower surface as the context of claim 1. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 2-11 and 14-16 depend on claim 1.
In addition, a closest prior art, Yoshimura et al. (US 2023/0420446), discloses a semiconductor device, comprising: a first ESD diode 4A (Fig. 9, paragraph 0095) connected between a first power supply pad 8 (Fig. 9, paragraph 0036) configured to receive a first power supply voltage (“5 V” in paragraph 0034) and a signal pad 7 (Fig. 9, paragraph 0094); and a second ESD diode 4B (Fig. 9, paragraph 0095) connected between a second power supply pad 9 (Fig. 9, paragraph 0036) configured to receive a second power supply voltage (“reference voltage” in paragraph 0034) and the signal pad 7 (Fig. 9), the second power supply voltage (“reference voltage” in paragraph 0034) having a level lower than a level of the first power supply voltage (“5 V” in paragraph 0034), wherein the first ESD diode 4A (Fig. 9) comprises a first impurity region 30A (Fig. 9, paragraph 0103) doped with N-type impurities (“n” in Fig. 9) and a second impurity region 40A (Fig. 9, paragraph 0103) doped with P-type impurities (“p” in Fig. 9), the second ESD diode 4B (Fig. 9) comprises a third impurity region 40B (Fig. 9, paragraph 0114) doped with N-type impurities (“n” in Fig. 9) and a fourth impurity region 30B (Fig. 9, paragraph 0114) doped with P-type impurities (“p” in Fig. 9), and the first to fourth impurity regions (30A, 40A, 40B, and 30B in Fig. 9) are formed in a well region (20A (Fig. 10A) and 20B (Fig. 11A), paragraphs 0103 and 0114) of a substrate 10 (Figs. 10A and 11A, paragraph 0083), and a lower surface of each of the first impurity region 30A (Fig. 10A) and the third impurity region 40B (Fig. 11A) has an uneven structure (see Fig. 10A and paragraph 0055, wherein “The first bottom wall portion 32A includes a curved portion that protrudes to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the curved portions together.”; and see Fig. 11A and paragraph 0083, wherein “The second bottom wall 43B includes an outer curved portion and an inner curved portion both of which protrude to a side opposite to the first principal surface 11 of the semiconductor layer 10 and a flat portion that connects the outer curved portion and the inner curved portion together.”) but fails to teach an uneven structure comprising projections with a first group of the projections extending vertically into the first impurity region from the lower surface of the first impurity region and a second group of the projections extending vertically into the third impurity region from a lowest extent of the lower surface of the third impurity region as the context of claim 17. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 18-20 depend on claim 17.
Response to Arguments
1. Applicant's arguments filed 5/28/2026 have been fully considered.
Applicant's arguments with respect to claims 21-22 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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