DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 19-22 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/23/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2,5-7,11,13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2013/0026623 A1 to Chen et al., “Chen”, in view of U.S. Patent Number 6,291,899 B1 to Wensel et al., “Wensel”.
Regarding claim 1, Chen discloses a package (Fig. 2, Fig. 6), comprising:
a semiconductor die (100, ¶ [0016]) having a device side in which circuitry (e.g. Fig. 6 conductive line 118, ¶ [0027]) is formed;
first (e.g. Fig. 2 one of 102/104 on left, ¶ [0017]) and second (e.g. one of 102/104 on right) metal members coupled to and extending away from the device side;
a passivation layer (Fig. 6 layer 120 and/or 122, ¶ [0027]) contacting the device side, at least a portion of the passivation layer [is] positioned between the first (102/104 on left) and second (102/104 on right) metal members, the passivation layer (120 and/or 122) including a top surface (downward facing surface when mounted) facing away from the semiconductor die (100); and
a passivation layer protrusion (106, ¶ [0018],[0019]) coupled to and extending away from the top surface (extends away from passivation 120 and/or 122), the passivation layer protrusion (106) having a height ranging from 0.5 microns to 50 microns (equal to bump height, ¶ [0018],[0028]).
Chen fails to clearly teach wherein the passivation layer protrusion (106) is formed of multiple passivation layer protrusions.
Wensel teaches (e.g. Fig. 4A,4B) wherein a protrusion (44A) is formed of multiple protrusions (interlacing structure surrounding bumps 38, multiple “arms”, column 4 lines 51-67).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the passivation layer protrusion of Chen as a lattice of connected protrusions as taught by Wensel in order to spread out the locations of the bumps and the passivation layer protrusion in order to desirably reduce package warpage (Wensel Abstract, column 1 lines 7-12, column 1 line 51 to column 2 line 40, column 5 line 64 to column 6 line 12) and/or require less protrusion material (Wensel column 4 line 55).
Regarding claim 2, Chen in view of Wensel yields the package of claim 1, and Wensel further teaches (FIG. 4B) wherein the multiple PLPs (44) form a lattice pattern (as pictured) on the top surface (when applied to Chen).
Regarding claim 5, Chen in view of Wensel yields the package of claim 1, and Wensel further teaches (FIG. 4B) wherein the multiple PLPs (lattice 44B) form a barrier to a direct line of sight between the first and second metal members (Wensel protrusions 44A block line of sight between bumps 38 when applied to Chen).
Regarding claim 6, although Chen in view of Wensel yields the package of claim 1, Chen in view of Wada fails to clearly teach wherein a pitch between the multiple PLPs ranges from 0.5 microns to 10 microns.
However, Chen teaches wherein a pitch (Fig. 6 pitch d3) between the spacer (106) and a metal member (bump 102/104/106) may be about 10 microns or less (¶ [0028]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Chen in view of Wensel with the pitch between the multiple passivation layer protrusions within the claimed range as suggested by the similar pitch of Chen since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the pitch determines the dimensions of the package and the resulting stress on the package (Chen ¶ [0004],[0035], Wensel column 1 lines 8-12, column 1 line 51 to column 2 line 33) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 7, Chen in view of Wensel yields the package of claim 1, and Chen in view of Wensel further yields wherein the multiple PLPs have cross-sections (as viewed from the side) that are shaped rectangles (Chen Fig. 2 cross-sectional side view of 106 is a rectangle, Wensel Fig. 4A cross-sectional side view of 44A are rectangles).
Regarding claim 11, Chen in view of Wensel yields the package of claim 1, and Chen further teaches wherein (e.g. Fig. 6) top surfaces (i.e. exposed surfaces) of the first and second metal members (bumps 102/104) are not covered by the passivation layer (120 and/or 122, not covered in order to provide electrical contacts).
Regarding claim 13, Chen in view of Wensel yields the package of claim 1, and Chen further teaches wherein the package is a wafer chip scale package (¶ [0021]).
Claims 1,5-7,11-13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2013/0026623 A1 to Chen et al., “Chen”, in view of U.S. Patent Application Publication Number 2018/0040525 A1 to Wada, “Wada”.
Regarding claim 1, Chen discloses a package (Fig. 2, Fig. 6), comprising:
a semiconductor die (100, ¶ [0016]) having a device side in which circuitry (e.g. Fig. 6 conductive line 118, ¶ [0027]) is formed;
first (e.g. Fig. 2 one of 102/104 on left, ¶ [0017]) and second (e.g. one of 102/104 on right) metal members coupled to and extending away from the device side;
a passivation layer (Fig. 6 layer 120 and/or 122, ¶ [0027]) contacting the device side, at least a portion of the passivation layer [is] positioned between the first (102/104 on left) and second (102/104 on right) metal members, the passivation layer (120 and/or 122) including a top surface (downward facing surface when mounted) facing away from the semiconductor die (100); and
a passivation layer protrusion (106, ¶ [0018],[0019]) coupled to and extending away from the top surface (extends away from passivation 120 and/or 122), the passivation layer protrusion (106) having a height ranging from 0.5 microns to 50 microns (equal to bump height, ¶ [0018],[0028]).
Chen fails to clearly teach wherein the passivation layer protrusion (106) is formed of multiple passivation layer protrusions.
Wada teaches wherein a single passivation protrusion (FIG. 4 protrusion 30a, ¶ [0073] or FIG. 5 protrusion 30b, ¶ [0080]) may be modified to be formed of a plurality of passivation protrusions (FIG. 1 protrusions 30, ¶ [0047]-[0051],[0069], FIG. 6 protrusions 30c, ¶ [0086]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Chen with the passivation layer protrusion being formed of a plurality of passivation layer protrusions as taught by Wada in order to allow for additional positional arrangement which allows for a high degree of freedom in position and consideration of the functional surface of the integrated circuit (IC) and/or avoid opening space (Wada ¶ [0089]) and achieve good flip chip mounting (Wada ¶ [0090]).
Regarding claim 5, Chen in view of Wada yields the package of claim 1, and Wada further teaches wherein the multiple PLPs (30,30c) form a barrier to a direct line of sight between the first and second metal members (e.g. bumps 23 along lines A-A’ or B-B’).
Regarding claim 6, although Chen in view of Wada yields the package of claim 1, Chen in view of Wada fails to clearly teach wherein a pitch between the multiple PLPs ranges from 0.5 microns to 10 microns.
However, Chen teaches wherein a pitch (Fig. 6 pitch d3) between the spacer (106) and a metal member (bump 102/104/106) may be about 10 microns or less (¶ [0028]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Chen in view of Wada with the pitch between the multiple passivation layer protrusions within the claimed range as suggested by the similar pitch of Chen since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the pitch determines the dimensions of the package and the resulting warpage (Chen ¶ [0004],[0035], Wada ¶ [0026],[0029],[0067]) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 7, Chen in view of Wada yields the package of claim 1, and Chen in view of Wada further yields wherein the multiple PLPs have cross-sections that are rectangles (Chen Fig. 2 cross-sectional side view of 106 is a rectangle, Wada FIG. 1(b) cross-sectional side view of 30 are rectangles).
Regarding claim 11, Chen in view of Wada yields the package of claim 1, and Chen further teaches wherein (e.g. Fig. 6) top surfaces (i.e. exposed surfaces) of the first and second metal members (bumps 102/104) are not covered by the passivation layer (120 and/or 122, not covered in order to provide electrical contacts).
Regarding claim 12, although Chen in view of Wada yields the package of claim 1, Chen fails to clearly state wherein the passivation layer (FIG. 6 layer 120 and/or 120) is composed of a first material together with the PLP (106, multiple when applying teachings of Wada) are composed of a second material that is different from the first material.
However, Chen teaches a variety of materials for the passivation layer protrusion (e.g. solder mask, resin, epoxy, or other materials (¶ [0019]) which would include combinations of materials different from the first material (of 120 and/or 122).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the package of Chen in view of Wada with the first and second materials being different as suggested by Chen in order to select materials which reduce warpage (Chen ¶ [0004],[0035]) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding claim 13, Chen in view of Wada yields the package of claim 1, and Chen further teaches wherein the package is a wafer chip scale package (¶ [0021]).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2013/0026623 A1 to Chen et al., “Chen”, in view of U.S. Patent Number 6,291,899 B1 to Wensel et al., “Wensel”, as applied to claim 1 above, and further in view of U.S. Patent Application Publication Number 2019/0157222 A1 to Lakhera et al., “Lakhera”.
Regarding claim 3, although Chen in view of Wensel yields the package of claim 1, Chen and Wensel fail to clearly teach wherein the multiple PLPs have widths ranging from 0.5 microns to 50 microns.
Lakhera teaches (e.g. FIG. 6) wherein an insulating protrusion has a width (640) of 5 to 100 microns (¶ [0023]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the package of Chen in view of Wensel with the protrusions having a width within the claimed range as exemplified by Lakhera in order to tune the dimensions depending on the size of the external connections being used (Lakhera ¶ [0023]) and/or achieve sufficient width to isolate joints and allow for RF devices without RF signal degradation (Lakhera ¶ [0010]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the width of the protrusions is determined by and determines the dimensions and size of the package making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 4, although Chen in view of Wensel yields the package of claim 1, wherein the multiple PLPs have lengths ranging from 0.5 microns to 50 microns.
Lakhera teaches (e.g. FIG. 6) wherein an insulating protrusion has a length (640) of 5 to 100 microns (¶ [0023]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the package of Chen in view of Wensel with the protrusions having a length within the claimed range as exemplified by Lakhera in order to tune the dimensions depending on the size of the external connections being used (Lakhera ¶ [0023]) and/or achieve sufficient width to isolate joints and allow for RF devices without RF signal degradation (Lakhera ¶ [0010]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the length of the protrusions is determined by and determines the dimensions and size of the package making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2013/0026623 A1 to Chen et al., “Chen”, in view of U.S. Patent Application Publication Number 2018/0040525 A1 to Wada, “Wada”, as applied to claim 1 above, and further in view of
U.S. Patent Application Publication Number 2023/0395482 A1 to Kim et al., “Kim”.
Regarding claim 8, although Chen in view of Wada yields the package of claim 1, Chen and Wada fail to clearly teach wherein the multiple PLPs are oriented differently in space.
Kim teaches (FIG. 6, ¶ [0033],[0034]) wherein a plurality of protrusions (302) are oriented differently in space (along directions D3 and D4).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the package of Chen in view of Wada with the protrusions oriented in different directions in space as taught by Kim in order to incorporate an under-fill material to increase structural stability (Kim ¶ [0004],[0005]) and oriented differently in order to desirably direct the under-fill to the corners of the chip (Kim ¶ [0034]).
Allowable Subject Matter
Claims 14-18 are allowed.
Claims 9-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art e.g. Chen teaches a passivation layer protrusion and prior art e.g. Wensel and Wada teach a plurality of protrusions as discussed above.
However, prior art fails to reasonably teach or suggest together the passivation layer including a first top surface facing away from the semiconductor die, the first and second metal members extending away from the device side and past the first top surface; multiple passivation layer protrusions arranged in a lattice pattern on the first top surface and extending away from the first top surface, the multiple passivation layer protrusions having heights ranging from 0.5 microns to 50 microns, widths ranging from 0.5 microns to 50 microns, lengths ranging from 0.5 microns to 50 microns, and a pitch ranging from 0.5 microns to 10 microns; a polyimide layer contacting the first top surface, at least a portion of the polyimide layer positioned between the first and second metal members, the polyimide layer including a second top surface facing away from the semiconductor die; and multiple polyimide layer protrusions arranged in a lattice pattern on the second top surface and extending away from the second top surface, the multiple polyimide layer protrusions having heights ranging from 0.5 microns to 50 microns, widths ranging from 0.5 microns to 50 microns, lengths ranging from 0.5 microns to 50 microns, and a pitch ranging from 0.5 microns to 10 microns, together with all of the other limitations of claim 14 as claimed. Claims 15-18 are allowable insofar as they depend upon and include all of the limitations of allowable claim 14.
Prior art additionally fails to clearly teach a polyimide layer contacting the top surface of the passivation layer, the polyimide layer having a top polyimide surface facing away from the semiconductor die, the top polyimide surface having multiple additional PLPs extending away from the top polyimide surface, as claimed in claim 9 together with all of the limitations of claim 1 as claimed. Claim 10 objected to as allowable insofar as it depends upon and includes all of the limitations of claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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/Eric A. Ward/Primary Examiner, Art Unit 2891
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