DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20200402999 (Nakaki).
Concerning claim 1, Nakaki discloses a memory device comprising (Figs. 20-28):
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a first conductive layer (22) ([0069]); a first conductive film (35) extending in a first direction (Z-direction) above the first conductive layer (Fig. 21 and [0078]); a first semiconductor film (29 +31) extending in the first direction between the first conductive layer and the first conductive film and intersecting the first conductive layer (Fig. 21 and [0078], note that the semiconductor film 29 extends into the first conductive layer 22 located beneath it); a second semiconductor film (33a + 33b + 33c) that is in contact with the first semiconductor film extends in the first direction between the first conductive layer and the first conductive film, and faces the first conductive film (Fig. 21 and [0076]); a first insulating film (26 +27+28) provided between the first conductive layer and the first semiconductor film ([0074]); and a second insulating film provided between the first conductive film and each of the first semiconductor film and the second semiconductor film (Fig. 21 and [0079]).
Continuing to claim 2, Nakaki discloses further comprising a second conductive layer (extension portion of 35) continuous with the first conductive film and extending in a second direction (X- direction) intersecting the first direction (Fig. 22, it is noted that the first conductive layer has a thickness that extends in the Z-direction and a length that extends in the X-direction, the examiner is interpreting the portion that extends in the Z-direction to be the first conductive film and the portion that extends in the X-direction to be the second conductive layer).
Considering claim 3, Nakaki discloses further comprising a first pillar (MP5) and a second pillar (MP7) (Figs. 20 and 22), each including the first conductive film, the first semiconductor film, the second semiconductor film, the first insulating film, and the second insulating film, the first pillar and the second pillar being arranged in the second direction, wherein the second conductive layer is continuous with both of the first conductive film of the first pillar and the first conductive film of the second pillar (Figs. 20 and22 and [0147]).
Referring to claim 4, Nakaki discloses further comprising a third pillar (MP6) and a fourth pillar (MP8), each including the first conductive film, the first semiconductor film, the second semiconductor film, the first insulating film, and the second insulating film, the third pillar and the fourth pillar being arranged in a third direction (Y-direction) intersecting the first direction and the second direction (Fig. 20), wherein the second conductive layer is continuous with both of the first conductive film of the third pillar and the first conductive film of the fourth pillar (Fig. 20 and [0134]).
Regarding claim 5, Nakaki discloses further comprising:
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a first semiconductor layer (rectangular encircled region in annotated Fig. 22 above) continuous with the second semiconductor film (oval encircled region in annotated Fig. 22 above) and extending in a third direction (A-direction) intersecting the first direction and the second direction ([0138]); a contact (37 + 38) that is in contact with an upper surface of the first semiconductor layer and extends in the first direction (Fig. 22); and a third conductive layer (39) that is in contact with an upper surface of the contact above the second conductive layer and extends in a fourth direction (Y-direction) intersecting the first direction and the second direction (Figs. 20 and 22 and [0087]).
Pertaining to claim 6, Nakaki discloses further comprising a third insulating film (25) provided between the second conductive layer and the contact ([0154]), wherein the contact includes a portion overlapping the third insulating film in plan view (Figs. 28).
As to claim 7, Nakaki discloses comprising a fifth pillar (MP6) and a sixth pillar (MP8), each including the first conductive film, the first semiconductor film, the second semiconductor film, the first insulating film, and the second insulating film, the third pillar and the fourth pillar being arranged in the third direction (A-direction) intersecting the first direction and the second direction (Fig. 20), wherein the second conductive layer is continuous with both of the first conductive film of the fifth pillar and the first conductive film of the sixth pillar (Fig. 20 and [0134]).
Concerning claim 8, Nakaki discloses wherein the first conductive film of the fifth pillar and the first conductive film of the sixth pillar are electrically insulated from each other (Fig. 22).
Continuing to claim 9, Nakaki discloses further comprising a seventh pillar including the first conductive film, the first semiconductor film, the second semiconductor film, the first insulating film, and the second insulating film, the seventh pillar being arranged along with the fifth pillar and the sixth pillar in the third direction, wherein the first semiconductor layer is further continuous with the second semiconductor film of the seventh pillar (Fig. 28 and [0134]).
Considering claim 10, Nakaki discloses wherein the sixth pillar is adjacent to the fifth pillar and the seventh pillar in the third direction, and the contact is in contact with an upper surface of a portion of the first semiconductor layer between the fifth pillar and the sixth pillar and an upper surface of a portion of the first semiconductor layer between the sixth pillar and the seventh pillar (Fig. 28 and [0134]).
Referring to claim 12, Nakaki discloses wherein the third direction and the fourth direction are parallel to each other ([0136]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200402999 (Nakaki).
Regarding claim 11, Nakaki discloses a third and a fourth direction .
Nakaki does not disclose in the embodiment as shown in Figs. 20 -28 wherein the third direction and the fourth direction intersect each other. However, Nakaki discloses several different embodiments (Fig. 4 and [0080]) in which the third and fourth directions intersect each other and has a crank shape or a bent shape in which the semiconductor layer 33a extending in the Y direction, the semiconductor layer 33b extending substantially in the Z direction, and the semiconductor layer 33c extending in the Y direction are connected together. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). See MPEP 2144.04 IV B. Therefore absent evidence that the claimed configuration is significant it would have been obvious to one of ordinary skill in the art to have the third and the fourth directions to intersect as disclosed in the other embodiments.
Claim(s) 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200402999 (Nakaki) as applied to claim 1 above, and further in view of US 20200303402 (Kobayashi et al).
Pertaining to claim 13, Nakaki discloses forming the second semiconductor film.
Nakaki does not disclose further comprising a fourth conductive layer and a fifth conductive layer provided above the first conductive layer and separated from each other, each intersecting the second semiconductor film and the first conductive film, wherein the second semiconductor film is provided between the first conductive film and each of the fourth conductive layer and the fifth conductive layer, and the first insulating film is provided between the second semiconductor film and each of the fourth conductive layer and the fifth conductive layer. However, Kobayashi discloses a memory configuration (Fig. 22) in which a fourth conductive layer (24) and a fifth conductive layer (24) provided above the first conductive layer and separated from each other (Fig. 22), each intersecting the second semiconductor film (42) and the first conductive film (Fig. 22 and [0092], Note that there are at least two conductive layers 24 and each are intersecting second semiconductor layer 42), wherein the second semiconductor film is provided between the first conductive film and each of the fourth conductive layer and the fifth conductive layer, and the first insulating film is provided between the second semiconductor film and each of the fourth conductive layer and the fifth conductive layer (Fig. 22). Kobayashi discloses that such configuration provide for semiconductor storage devices capable of improved connection between a select gate line and a contact ([0047]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Nakaki in view of Kobayashi such that a fourth conductive layer and a fifth conductive layer provided above the first conductive layer and separated from each other, each intersecting the second semiconductor film and the first conductive film, wherein the second semiconductor film is provided between the first conductive film and each of the fourth conductive layer and the fifth conductive layer, and the first insulating film is provided between the second semiconductor film and each of the fourth conductive layer and the fifth conductive layer so as to provide a semiconductor storage device capable of improved connection between a select gate line and a contact.
As to claim 14, Nakaki in view of Kobayashi disclose wherein the first semiconductor film and the second semiconductor film are continuous with each other (Nakaki Fig. 21).
Concerning claim 15, Nakaki in view of Kobayashi disclose further comprising a row decoder (Nakaki 15) configured to independently apply a voltage to the fourth conductive layer and the fifth conductive layer (Nakaki [0069]).
Continuing to claim 16, Nakaki in view of Kobayashi disclose wherein the fourth conductive layer is provided between the first conductive layer and the fifth conductive layer, and the row decoder is configured to apply a first voltage to the fourth conductive layer and apply a second voltage lower than the first voltage to the fifth conductive layer in a write operation and a read operation (Nakaki [0034]).
Considering claim 17, Nakaki in view of Kobayashi disclose further comprising: a fifth pillar and a sixth pillar, each including the first conductive film, the first semiconductor film, the second semiconductor film, the first insulating film, and the second insulating film, and arranged in a third direction intersecting the first direction; a second conductive layer continuous with the first conductive film of the fifth pillar and extends in a second direction intersecting the first direction and the third direction; a sixth conductive layer continuous with the first conductive film of the sixth pillar and extending in the second direction; and a row decoder configured to independently apply a voltage to the first conductive film of the fifth pillar and the first conductive film of the sixth pillar, wherein the row decoder is configured to apply a third voltage to the first conductive film of the fifth pillar and apply a fourth voltage lower than the third voltage to the first conductive film of the sixth pillar during a write operation and a read operation (Nakaki [0034]-[0035]).
Referring to claim 18, Nakaki in view of Kobayashi disclose wherein the first insulating film includes a charge storage film ([0048]-[0049]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20200075622 discloses a memory device (Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/VALERIE N NEWTON/ Examiner, Art Unit 2897 02/21/26