DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 objected to because of the following informalities:
Claim 1 line 17 ends with “layers” which should be “layers;” to separate the language about forming the second local liner from the exposing of the bottom sacrificial layer of line 18.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2,4 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0074809 A1 to Xie et al., “Xie”, in view of U.S. Patent Application Publication Number 2023/0197831 A1 to Chan et al., “Chan”.
Regarding claim 1, Xie discloses a method of manufacturing an integrated circuit device, the method comprising:
forming (FIG. 2) a fin-type active region (115, ¶ [0049]) on a substrate (110, ¶ [0034]);
forming, on the fin-type active region, a stack structure (133, ¶ [0049]) in which a plurality of sacrificial semiconductor layers (132) and a plurality of nanosheet semiconductor layers (142) are alternately stacked one-by-one;
forming (FIG. 7) a first local liner (190, ¶ [0067]) on a sidewall of the stack structure to cover a sidewall of a bottom sacrificial semiconductor layer (122), the bottom sacrificial semiconductor layer (122) being a sacrificial semiconductor layer closest to the fin-type active region (115) from among the plurality of sacrificial semiconductor layers, and (FIG. 7) expose sidewalls of other sacrificial semiconductor layers (132), the other sacrificial semiconductor layers (132) being sacrificial semiconductor layers except for the bottom sacrificial semiconductor layer (122) from among the plurality of sacrificial semiconductor layers;
exposing (FIG. 12) the bottom sacrificial semiconductor layer by removing the first local liner (“the plug(s) 190 can be removed using a selective isotropic etch to expose portions of the bottom sacrificial segment 122, and the bottom sacrificial segment 122 can be removed using a subsequent isotropic etch” ¶ [0077]);
forming (e.g. FIG. 12) a bottom insulating space (195, ¶ [0077]) to expose a fin top surface of the fin-type active region (115) by removing the bottom sacrificial semiconductor layer; and
forming (FIG. 14) a bottom insulating structure (220, ¶ [0081]) to fill the bottom insulating space.
Xie fails to clearly teach forming a second local liner on the sidewall of the stack structure to cover sidewalls of the other sacrificial semiconductor layers.
Chan teaches (Fig. 4, Fig. 5) forming a second local liner (140, ¶ [0085]) on sidewall of a stack structure (111) to cover sidewalls of other sacrificial layers (114, ¶ [0105]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Xie by adding a second local liner on the upper sacrificial layers as taught by Chan by allowing for more freely selecting the selectivity of the etch for the lower sacrificial layer (Chan ¶ [0023]).
Regarding claim 2, although Xie in view of Chan yields the method of claim 1, Xie fails to clearly teach wherein the first local liner and the second local liner comprise different materials from each other.
However, Chan teaches (Fig. 4 to Fig. 5) wherein a first element (130) is etched selectively to the second local liner (140) using e.g. a wet etching process (¶ [0123]) which inherently requires the first and second materials (of 130 and 140) to be different to be selectively etched.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Xie in view of Chan using different materials as taught by Chan in order to selectively etch the first or lower local liner to selectively etch the first or lower local liner (Chan ¶ [0085],[0086]).
Regarding claim 4, although Xie in view of Chan yields the method of claim 1, Xie fails to clearly teach wherein a thickness of the second local liner is less than a thickness of the first local liner.
However, Chan shows in the drawings (e.g. Fig. 4) wherein a thickness of a second local liner (140) is less than a first structure (130) and is formed by atomic layer deposition (ALD) ( ¶ [0122]) which is known to produce thin highly conformal layer.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Xie in view of Chan with the relative thicknesses as claimed as suggested by Chan since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the liner thickness determines its time resistance to etching making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0074809 A1 to Xie et al., “Xie”, in view of U.S. Patent Application Publication Number 2023/0197831 A1 to Chan et al., “Chan”, as applied to claim 1 above, and further in view of U.S. Patent Number 10,263,100 B1 to Bi et al., “Bi”.
Regarding claim 3, Xie in view of Chan yields the method of claim 1, and Xie further teaches wherein each of the plurality of sacrificial semiconductor layers comprises a SiGe layer (¶ [0039]).
Although Xie uses the same reference number (130) for each of the sacrificial semiconductor layers, Xie fails to expressly state wherein respective Ge contents of the plurality of sacrificial semiconductor layers (130) are equal to each other.
Bi teaches (e.g. FIG. 2) wherein Ge contents of a plurality of sacrificial layers (114, 116, 118) are equal to each other (25%, column 9 lines 22-61, equal to each other since including REO layers 132, 134, 136, 138, 139).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Xie in view of Chan with equal Ge sacrificial layers bounded by REO layers as taught by Bi in order to form uniform etched cavities without unintentional (and undesirable) diffusion or unwanted voids (Bi column 9 lines 23-41).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0074809 A1 to Xie et al., “Xie”, in view of U.S. Patent Application Publication Number 2023/0197831 A1 to Chan et al., “Chan”, further in view of U.S. Patent Number 10,263,100 B1 to Bi et al., “Bi”.
Regarding claim 19, Xie discloses a method of manufacturing an integrated circuit device, the method comprising:
alternately stacking (FIG. 1) a plurality of sacrificial semiconductor layers (130, ¶ [0039]) and a plurality of nanosheet semiconductor layers (140 ¶ [0042]) one-by-one on a substrate, each of the plurality of sacrificial semiconductor layers comprising a SiGe layer (¶ [0039]), and each of the plurality of nanosheet semiconductor layers comprising a Si layer (¶ [0042]);
forming (FIG. 2) a stack structure and a fin-type active region (115, ¶ [0049]), which has a fin top surface covered by the stack structure, by partially etching (patterning ¶ [0047]) each of the plurality of sacrificial semiconductor layers (130), the plurality of nanosheet semiconductor layers (140), and the substrate (110), the stack structure comprising a portion of each of the plurality of sacrificial semiconductor layers and the plurality of nanosheet semiconductor layers;
forming (FIG. 4) a device isolation film (160 and/or 170 and/or 182, ¶ [0051]-[0058]) to cover sidewalls of the fin-type active region;
forming (FIG. 7) a first local liner (190, ¶ [0067]) on a sidewall of the stack structure to cover a sidewall of a bottom sacrificial semiconductor layer (122), the bottom sacrificial semiconductor layer (122) being a sacrificial semiconductor layer closest to the fin-type active region (115), from among the plurality of sacrificial semiconductor layers, and expose sidewalls (as pictured) of the other sacrificial semiconductor layers (132), the other sacrificial semiconductor layers (132) being sacrificial semiconductor layers except for the bottom sacrificial semiconductor layer (122), from among the plurality of sacrificial semiconductor layers;
exposing (FIG. 12) the bottom sacrificial semiconductor layer by removing the first local liner (“the plug(s) 190 can be removed using a selective isotropic etch to expose portions of the bottom sacrificial segment 122, and the bottom sacrificial segment 122 can be removed using a subsequent isotropic etch” ¶ [0077]);
forming (e.g. FIG. 12) a bottom insulating space (195, ¶ [0077]) to expose the fin top surface of the fin-type active region (115) by removing the bottom sacrificial semiconductor layer; and
forming (FIG. 14) a bottom insulating structure (220, ¶ [0081]) to fill the bottom insulating space.
Although Xie uses the same reference number (130) for each of the sacrificial semiconductor layers, Xie fails to expressly state wherein respective Ge contents of the plurality of sacrificial semiconductor layers (130) are equal to each other.
Bi teaches (e.g. FIG. 2) wherein Ge contents of a plurality of sacrificial layers (114, 116, 118) are equal to each other (25%, column 9 lines 22-61, equal to each other since including REO layers 132, 134, 136, 138, 139).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Xie with equal Ge sacrificial layers bounded by REO layers as taught by Bi in order to form uniform etched cavities without unintentional (and undesirable) diffusion or unwanted voids (Bi column 9 lines 23-41).
Xie fails to clearly teach forming a second local liner on the sidewall of the stack structure to cover the sidewalls of the other sacrificial semiconductor layers.
Chan teaches (Fig. 4, Fig. 5) forming a second local liner (140, ¶ [0085]) on sidewall of a stack structure (111) to cover sidewalls of other sacrificial layers (114, ¶ [0105]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Xie by adding a second local liner on the upper sacrificial layers as taught by Chan by allowing for more freely selecting the selectivity of the etch for the lower sacrificial layer (Chan ¶ [0023]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0074809 A1 to Xie et al., “Xie”, in view of U.S. Patent Application Publication Number 2023/0197831 A1 to Chan et al., “Chan”, U.S. Patent Number 10,263,100 B1 to Bi et al., “Bi”, as applied to claim 19 above, further in view of U.S. Patent Application Publication Number 2021/0305420 A1 to Frougier et al., “Frougier”.
Regarding claim 20, Xie in view of Chan and Bi yields the method of claim 19, and Chan further teaches wherein the second local liner (140) comprises a second insulating film comprising no nitrogen atoms (e.g. silicon oxide ¶ [0122]).
Xie fails to clearly teach wherein the first local liner comprises a first insulating film comprising nitrogen atoms.
Frougier teaches (FIG. 4C) wherein a first local liner (402) comprises a first insulating film comprising nitrogen atoms (e.g. ssiliconborocarbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon oxynitride (SiON), ¶ [0048]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Xie in view of Chan and Bi by using a nitrogen containing material as taught by Frougier
and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Allowable Subject Matter
Claims 12-18 are allowed.
Claims 5-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Although prior art e.g. Xie teaches forming a first local liner and Chan teaches forming a second local liner as discussed above, prior art fails to reasonably teach or suggest forming a bottom insulating structure between the fin top surface of the fin-type active region and the nanosheet stack, a source/drain region arranged on the fin-type active region and contacting the plurality of nanosheets and the bottom insulating structure, and a gate line surrounding the plurality of nanosheets;
removing the substrate from a backside surface of the substrate; exposing the bottom insulating structure by removing the fin-type active region by using the bottom insulating structure as an etch stop film; and forming a backside structure on the bottom insulating structure, wherein the forming of the frontside structure comprises, forming, on the fin-type active region, a stack structure in which a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers are alternately stacked one-by-one, together with all of the other limitations of the method of claim 12. Claims 13-18 are allowable insofar as they depend upon and include all of the limitations of allowable claim 12.
Conclusion
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/Eric A. Ward/Primary Examiner, Art Unit 2891