Prosecution Insights
Last updated: April 19, 2026
Application No. 18/497,525

LIGHT EMITTING DIODE

Non-Final OA §103§112
Filed
Oct 30, 2023
Examiner
SQUIRES, BRETT STEPHEN
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan-Asia Semiconductor Corporation
OA Round
1 (Non-Final)
47%
Grant Probability
Moderate
1-2
OA Rounds
3y 6m
To Grant
92%
With Interview

Examiner Intelligence

Grants 47% of resolved cases
47%
Career Allow Rate
22 granted / 47 resolved
-21.2% vs TC avg
Strong +45% interview lift
Without
With
+45.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
23 currently pending
Career history
70
Total Applications
across all art units

Statute-Specific Performance

§101
3.5%
-36.5% vs TC avg
§103
41.6%
+1.6% vs TC avg
§102
23.0%
-17.0% vs TC avg
§112
31.0%
-9.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 47 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS)s submitted on October 30, 2023, January 7, 2025, February 25, 2025, and October 24, 2025 were filed before the mailing of a first Office action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Specification The disclosure is objected to because of the following informalities: the paragraphs in the specification are not consecutively numbered. The examiner notes that the first paragraph in the specification under the heading Cross-References to Related Applications is not numbered and the last paragraph in specification is numbered with the number 1. Appropriate correction is required. Claim Objections Claim 4 is objected to because of the following informalities: clam 4 recites the limitation “the outer edge,” on page 1 line 21, this limitation lacks antecedent basis. This limitation is understood to be an outer edge. Appropriate correction is required. Claims 5-7 are objected to because of the following informalities: clam 5 recites the limitation “the third semiconductor layers,” on page 2 lines 3-4, this limitation appears to contain a typographical error because claim 5 previously recites “a third semiconductor layer,” on page 2 line 3. This limitation is understood to be the third semiconductor layer. Appropriate correction is required. Claims 6-7 are also objected to for containing the same limitation because claims 6-7 depend from claim 5. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 recites the limitation “wherein a wavelength of the light emitting layer is ranging from 1000 nanometers (nm) to 2000 nm,” on page 2 lines 15-16. This limitation renders the claim indefinite because it is unclear how this limitation further defines the structure of the light emitting layer. The examiner notes that wavelength is a property of the light emitted by the light emitting layer and is not a property of the light emitting layer itself. For examination purposes, this limitation will be interpretated as reciting the light emitting layer is configured to emit light having a wavelength in a range from 1000 nanometers (nm) to 2000 nm. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ito (JP 2020065041 A) in view of Meng et al. (US 2018/0351045). The examiner notes the that citations to paragraphs of Ito refer to the attached English language translation of Ito. Regarding Claim 1: Ito discloses a light emitting diode, comprising: an epitaxial composite layer (compound semiconductor layer formed by epitaxial growth, See figs. 9, 10A, ref. no. 7 and paragraphs 62-63); a dielectric layer (insulating layer, See figs. 9, 10A, ref. no. 42 and paragraph 63), the epitaxial composite layer being disposed on the dielectric layer (the compound semiconductor layer is formed on the insulating layer, See fig. 9, ref. nos. 7, 42); a transparent conductive layer (light transmitting conductive layer, See fig. 9, 10B, ref. no. 6, paragraphs 26 and 64), the dielectric layer being disposed on the transparent conductive layer (the insulating layer is formed on the light transmitting conductive layer, See fig. 9, ref. nos. 6, 42); and a metal layer (metal layer, See figs. 9, 10E, ref. no. 5 and paragraphs 65-66), wherein the transparent conductive layer is disposed on the metal layer (the light transmitting conductive layer is formed on the metal layer, See fig. 9, ref. nos. 5, 6). Ito does not disclose an outer edge of the transparent conductive layer is covered by the metal layer. Meng discloses an outer edge of the transparent conductive layer is covered by the metal layer (side surfaces of a transparent conductive adhesive layer are covered by a protective layer, See fig. 15, ref. nos. 425, 440, and paragraph 121). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the light emitting diode of Ito to include an outer edge of the transparent conductive layer is covered by the metal layer as taught by Meng in order to protect the light transmitting conductive layer from damage. (The examiner notes that the purpose of protective layer, protecting covered layers, is implicit the through the naming convention Meng chose for this layer.) Regarding Claim 2: Ito discloses wherein the transparent conductive layer further comprises a plurality of dotted transparent electrodes (contact portions of the light-transmitting layer surround by the insulating layer, See fig. 9, ref. nos. 42, 44 and paragraphs 60-61,) each of the dotted transparent electrodes is surrounded by the dielectric layer. Regarding Claim 3: Ito discloses wherein a material of the transparent conductive layer is one of indium tin oxide (indium tin oxide, See paragraph 26), aluminum zinc oxide, tin zinc oxide, zinc oxide (zinc oxide, See paragraph 26), nickel oxide, cadmium tin oxide, antimony tin oxide and a combination thereof. (The examiner also notes that the applicant has created a genus of equivalency among the recited materials with each material being obvious over the others.) Regarding Claim 4: The above stated combination of Ito and Meng discloses the above stated light emitting diode. The above stated combination of Ito and Meng does not disclose the outer edge of the dielectric layer is covered by the metal layer. Meng discloses an outer edge of the transparent conductive layer is covered by the metal layer (side surfaces of a multiple layers are covered by a protective layer, See fig. 15, ref. nos. 425, 426, 440, and paragraph 121). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the light emitting diode of Ito and Meng to include the outer edge of the dielectric layer is covered by the metal layer as taught by Meng in order to protect the insulating layer from damage. (The examiner notes that the purpose of protective layer, protecting covered layers, is implicit the through the naming convention Meng chose for this layer.) Regarding Claim 5: Ito discloses the epitaxial composite layer further comprises a first semiconductor layer (n-type semiconductor layer, See fig. 9, ref. no. 14 and paragraph 27), a light emitting layer (emission layer, See fig. 9, 10A, ref. no. 12 and paragraph 63), a second semiconductor layer (p-type cladding layer, See fig. 9, ref. no. 17 and paragraph 63), and a third semiconductor layer (p-type contact layer and p-type window layer, See fig 9, 10A, ref. nos. 13, 15, 16, paragraph 63), wherein the third semiconductor layers is disposed on the dielectric layer and electrically connected to the transparent conductive layer (the p-type contact layer is formed directly on the insulating layer and is in electrical contact with the contact portions of light-transmitting layer, See fig. 9, ref. nos. 15, 42, 44), the second semiconductor layer is disposed on the third semiconductor layer (the p-type cladding layer is formed on the p-type window layer, See fig. 9, ref. nos. 16, 17), and wherein the light emitting layer is disposed on the second semiconductor layer (the emission layer is formed on the p-type cladding layer, See fig. 9, ref. nos. 12, 17), and the first semiconductor layer is disposed on the light emitting layer (the n-type semiconductor layer is formed on the emission layer, See fig. 9, ref. nos. 12, 14). Regarding Claim 8: Ito discloses an upper electrode (cathode electrode layer formed on the compound semiconductor layer does not overlap the contact portions of the light-transmitting layer, See fig. 9 ref. nos. 7, 11, 44, paragraphs 61 and 68-69) disposed on the epitaxial composite layer without overlapping the dotted transparent electrodes. Regarding Claim 9: Ito discloses wherein a material of the metal layer is one of gold (Au) (Au, See paragraphs 64-65), silver (Ag), aluminum (Al), beryllium gold (BeAu) (an alloy containing Au, See paragraphs 64-65), germanium gold (GeAu) (an alloy containing Au, See paragraphs 64-65), and a combination thereof. (The examiner also notes that the applicant has created a genus of equivalency among the recited materials with each material being obvious over the others.) Regarding Claim 10: Ito discloses a substrate (Substrate, See fig. 9, 10D, ref. no. 2 and paragraphs 65-66) bonding with the metal layer. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ito (JP 2020065041 A) in view of Meng et al. (US 2018/0351045) further in view of Fuchida (WO 2023/144960 A1). The examiner notes that the citations to paragraphs of Fuchida refer to paragraphs in the attached English language translation of Fuchida. Regarding Claim 6: The above stated combination of Ito and Meng discloses the above stated light emitting diode. The examiner notes that Meng discloses epitaxially growing the compound semiconductor layer in paragraph 63. The above stated combination of Ito and Meng does not disclose herein the first semiconductor layer is an N-type indium phosphide (InP) layer, the second semiconductor layer is a P-type indium phosphide layer, and the third semiconductor layer is a P-type indium gallium arsenide (InGaAs) layer. Fuchida discloses herein the first semiconductor layer is an N-type indium phosphide (InP) layer (n-type InP substrate, See fig. 3, ref. no. 1, paragraphs 13 and 19), the second semiconductor layer is a P-type indium phosphide layer (p-type InP cladding layer, See fig. 3, ref. no. 5, paragraphs 13 and 19), and the third semiconductor layer is a P-type indium gallium arsenide (InGaAs) layer (p-type InGaAs contact layer, See fig. 3, ref. no. 6, paragraphs 13 and 19). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the light emitting diode of Ito and Meng to include the first semiconductor layer is an N-type indium phosphide (InP) layer, the second semiconductor layer is a P-type indium phosphide layer, and the third semiconductor layer is a P-type indium gallium arsenide (InGaAs) layer as taught by Fuchida since it has been held that the selection of a known material on the basis of its suitability for its intended use is a matter of obvious design choice. See In re Leshin, 125 USPQ 416 (CCPA 1960). 12. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ito (JP 2020065041 A) in view of Meng et al. (US 2018/0351045) further in view of Raring (US 2021/0194206). Regarding Claim 6: The above stated combination of Ito and Meng discloses the above stated light emitting diode. The above stated combination of Ito and Meng does not disclose wherein a wavelength of the light emitting layer is ranging from 1000 nanometers (nm) to 2000 nm. Raring discloses a wavelength of the light emitting layer is ranging from 1000 nanometers (nm) to 2000 nm (a laser diode operates with wavelength in the 1100nm to 2500nm range, See paragraph 54). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the light emitting diode of Ito and Meng to include operating with wavelength in 1100nm to 2500nm range as taught by Raring in order to provide eye-safe infrared illumination. (See Raring paragraph 54.) Conclusion 13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRETT SQUIRES whose telephone number is (571)272-8214. The examiner can normally be reached Mon-Fri 8:00am-5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899 /B.S./Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Oct 30, 2023
Application Filed
Feb 18, 2026
Non-Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 9325173
UTILIZATION OF DISTRIBUTED GENERATOR INVERTERS AS STATCOM
2y 5m to grant Granted Apr 26, 2016
Patent 9287703
GENERALIZED SYSTEM ARCHITECTURE FOR PERIPHERAL CONNECTIVITY AND CONTROL
2y 5m to grant Granted Mar 15, 2016
Patent 9281708
DEVICE FOR INDUCTIVE TRANSMISSION OF ELECTRICAL ENERGY
2y 5m to grant Granted Mar 08, 2016
Patent 9276428
SYSTEM POWER INTEGRATED CIRCUIT AND ARCHITECTURE, MANAGEMENT CIRCUIT, POWER SUPPLY ARRANGEMENT, AND PORTABLE APPARATUS
2y 5m to grant Granted Mar 01, 2016
Patent 9220179
Pluggable Power Cell For An Inverter
2y 5m to grant Granted Dec 22, 2015
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
47%
Grant Probability
92%
With Interview (+45.1%)
3y 6m
Median Time to Grant
Low
PTA Risk
Based on 47 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month