DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, Claims 1-6 and 9-20 ( claim 7 is not part of Species A because the protective fill structure is directly below the semiconductor die ) in the reply filed on 03/09/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102 as being anticipated by Yamazaki et al. ( US 2024/0395974 A1; hereinafter Yamazaki (‘974))
Regarding claim 1, Yamazaki (‘974) teaches a semiconductor device assembly ( [0084] In the display apparatus of one embodiment of the present invention, a semiconductor layer and an electrode included in the light-emitting device can be formed by a photolithography method ), comprising: a substrate ( Fig. 34 substrate 301 ) comprising: an insulator layer ( Fig. 34 insulating layer 125 ); a circuit layer ( Fig. 34 layer 101 ) below the insulator layer ( Fig. 34 #125 ) and comprising: a circuit structure ( Fig. 34 transistor 310 ); an isolation region ( Fig. 34 element isolation layer 315 ) adjacent to the circuit structure ( as shown in Fig. 34 ); and a protective fill structure ( Fig. 34 insulating layer 127 ) in the isolation region ( vertically above Fig. 34 #315 ); and a semiconductor die ( Fig. 40 IC 173 ) electrically connected to the substrate ( Fig. 40 substrate 152 ) via a plurality of electrical connections ( Fig. 40 connection portion 140 ).
Claims 18-20 are rejected under 35 U.S.C. 102 as being anticipated by Sharma et al. ( US 2024/0222272 A1; hereinafter Sharma (‘272) )
Regarding claim 18, Sharma (‘272) teaches a method, comprising: forming a conductive structure ( Fig. 9 metallization layer 908 ); forming an insulator layer ( Fig. 9 dielectric layers 909 ) above the conductive structure ( Fig. 9 #908 ); forming a solder resist layer ( Fig. 9 solder resist 913 ) above the insulator layer ( Fig. 9 #909 ); forming an opening through the solder resist layer ( as shown in Fig. 9 ) and the insulator layer ( Fig. 9 #909 ); and forming a protective fill structure in the opening ( Fig. 9 #940 ) and adjacent to an end of the conductive structure ( Fig. 9 #908 ).
Regarding claim 19, Sharma (‘272) teaches the method of claim 18 (as discussed above), wherein forming the protective fill structure in the opening ( Fig. 9 #940 ) and adjacent to the end of the conductive structure ( Fig. 9 #908 ) comprises: forming an amount of the protective fill structure that covers the end of the conductive structure ( [0076] An underfill layer may also partially embed the dies and surround interconnects below the dies, exemplary structures of which are described above ).
Regarding claim 20, Sharma (‘272) teaches the method of claim 18 ( as discussed above ), wherein forming the opening through the solder resist layer ( Fig. 9 #913 ) and the insulator layer ( Fig. 9 #909 ) comprises: performing an etch-back operation to form the opening ( [0094] In one embodiment, different hardmask, capping or plug materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under U.S.C. 103 as being unpatentable over Yamazaki et al.; US 2024/0395974 A1; 09/2022 in view of Yuda et al.; US 2024/0074170 A1; 08/2022
Claim 2: Yamazaki (‘974) discloses the semiconductor device assembly of claim 1 ( as discussed above ).
Yamazaki (‘974) does not appear to disclose the protective fill structure passes at least partially through the insulator layer.
However, Yuda teaches the protective fill structure ( Fig. 8F memory opening fill structure 58 ) passes at least partially through the insulator layer ( Fig. 8F insulating layers #32 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yuda with Yamazaki to implement the protective fill structure passes at least partially through the insulator layer because this approach would improve structural integrity of the assembly.
Claim 3: Yamazaki (‘974) discloses the semiconductor device assembly of claim 1 ( as discussed above ).
Yamazaki (‘974) does not appear to disclose the protective fill structure passes entirely through the insulator layer.
However, Yuda teaches the protective fill structure ( Fig. 8F memory opening fill structure 58 ) passes entirely through the insulator layer ( Fig. 8F insulating layers #32 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yuda with Yamazaki to implement the protective fill structure passes entirely through the insulator layer because this would provide direct, high-strength structural, thermal, and environmental protection to the most delicate parts of the assembly.
Claim 4 is rejected under U.S.C. 103 as being unpatentable over Yamazaki et al.; US 2024/0395974 A1; 09/2022 in view of Sutardja et al.; US 8,946,890 B2; 10/2011
Claim 4: Yamazaki (‘974) discloses the semiconductor device assembly of claim 1 ( as discussed above ).
Yamazaki (‘974) does not appear to disclose the circuit structure corresponds to a ground plane structure, and wherein the protective fill structure is configured to protect an end of the ground plane structure or an end of a power plane structure from corrosion or oxidation.
However, Sutardja teaches the circuit structure ( Fig. 3: electronic package assembly 300 ) corresponds to a ground plane structure ( Fig. 3 first metal layer 110 ), and wherein the protective fill structure ( Fig. 3 molding compound 306 ) is configured to protect an end of the ground plane structure ( Fig. 3 #110 ) or an end of a power plane structure ( Fig. 3: second metal layer 118 ) from corrosion or oxidation ( Col. 6 lines 36 – 42 The molding compound 306 generally comprises an electrically insulative material, such as a thermosetting resin, that is disposed to protect the semiconductor die 104 from moisture, oxidation, or chipping associated with handling. In another embodiment, the molding compound 306 is disposed to substantially fill a region between the second metal layer 118 and another die ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Sutardja with Yamazaki to implement the circuit structure corresponds to a ground plane structure, and wherein the protective fill structure is configured to protect an end of the ground plane structure or an end of a power plane structure from corrosion or oxidation because the protective fill structure is typically an encapsulation or conformal coating that covers the exposed edges of metal planes to provide corrosion and oxidation protection, EMI shielding and signal integrity and mechanical integrity and reliability.
Claims 5-6 are rejected under U.S.C. 103 as being unpatentable over Yamazaki et al.; US 2024/0395974 A1; 09/2022 in view of Yamazaki et al.; US 2022/0131010 A1; 02/2020
Claim 5: Yamazaki (‘974) discloses the semiconductor device assembly of claim 1 ( as discussed above ).
Yamazaki (‘974) does not appear to disclose the circuit structure corresponds to a data transmission structure, and wherein the protective fill structure is configured to protect an end of the data transmission structure or an end of or a clocking structure from corrosion or oxidation.
However, Yamazaki (‘010) teaches the circuit structure ( Fig. 22D: portable information terminal 9200 ) corresponds to a data transmission structure ( Fig. 20D: connection terminal 9006; [0499] The connection terminal 9006 of the portable information terminal 9200 allows mutual data transmission with another information terminal and charging ), and wherein the protective fill structure ( [0369] The protection layer 749 is attached to the sealing layer 732. A glass substrate, a resin film, or the like can be used as the protection layer 749. As the protection layer 749, an optical member such as a polarizing plate (including a circularly polarizing plate) or a scattering plate, an input device such as a touch sensor panel, or a structure in which two or more of these are stacked may be employed. Furthermore, the protection layer 749 may include a component included in part of a housing of an electronic device (for example, a portion to be a screen)) is configured to protect an end of the data transmission structure ( Fig. 22D connection terminal 9006 ) or an end of or a clocking structure from corrosion or oxidation ( [0371] it is preferable that inorganic insulating films with a high barrier property against impurities such as water be used as the insulating layer 741a and the insulating layer 741c ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yamazaki (‘010) with Yamazaki (‘974) to implement the circuit structure corresponds to a data transmission structure, and wherein the protective fill structure is configured to protect an end of the data transmission structure or an end of or a clocking structure from corrosion or oxidation because this approach improves signal integrity and high-speed communication.
Claim 6: Yamazaki (‘974) discloses the semiconductor device assembly of claim 1 ( as discussed above ).
Yamazaki (‘974) does not appear to disclose the circuit structure is a first circuit structure, and wherein the semiconductor device assembly further comprises: a second circuit structure, wherein the protective fill structure is between a first end of the first circuit structure and a second end of the second circuit structure.
However, Yamazaki (‘010) teaches the circuit structure is a first circuit structure ( Fig. 15: circuit portions 763 ), and wherein the semiconductor device assembly ( Fig. 15: display device 700 ) further comprises: a second circuit structure ( Fig. 15: display portion 702 ), wherein the protective fill structure ( Fig. 15: sealing layer 732 ) is between a first end of the first circuit structure ( Fig. 15 #763 ) and a second end of the second circuit structure ( Fig. 15 #702 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yamazaki (‘010) with Yamazaki (‘974) to implement the circuit structure is a first circuit structure, and wherein the semiconductor device assembly further comprises: a second circuit structure, wherein the protective fill structure is between a first end of the first circuit structure and a second end of the second circuit structure because this provided mechanical support, stress relieve, and electrical isolation.
Claim 9 is rejected under U.S.C. 103 as being unpatentable over Yamazaki et al.; US 2024/0395974 A1; 09/2022 in view of Park et al.; US 2025/0203761 A1; 11/2022
Claim 9: Yamazaki (’974 ) discloses the semiconductor device assembly of claim 1 ( as discussed above).
Yamazaki (‘974) does not appear to disclose the protective fill structure comprises a polymer material, and wherein the polymer material is included in an epoxy material or a solder resist material.
However, Park teaches the protective fill structure ( Fig. 2a: first protective layer 161 ) comprises a polymer material ( [0212] For example, the first protective layer 161 and the second protective layer 162 may be solder resist layers including an organic polymer material ), and wherein the polymer material is included in an epoxy material or a solder resist material ( as discussed above ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Park with Yamazaki (‘974) to implement the protective fill structure comprises a polymer material, and wherein the polymer material is included in an epoxy material or a solder resist material because this approach provides essential mechanical, thermal, and electrical protection.
Claim 10 is rejected under U.S.C. 103 as being unpatentable over Yamazaki et al.; US 2024/0395974 A1; 09/2022 in view of Sharma et al.; US 12,616,060 B2; 02/2022
Claim 10: Yamazaki (‘974 ) discloses the semiconductor device assembly of claim 1 ( as discussed above ).
Yamazaki (‘974 ) does not appear to disclose the semiconductor die is a non-volatile memory semiconductor die or a volatile memory semiconductor die, and wherein the semiconductor device assembly further comprises: a controller communicatively coupled to the semiconductor die via the substrate.
However, Sharma (‘060) teaches the semiconductor die is a non-volatile memory semiconductor die or a volatile memory semiconductor die ( Fig. 14: memory dies of the memory 1904 ), and wherein the semiconductor device assembly further comprises: a controller ( Fig. 14: logic circuitry 1902 ) communicatively coupled to the semiconductor die ( Col. 35 lines the semiconductor die is a non-volatile memory semiconductor die or a volatile memory semiconductor die ( Col.35 lines 19 – 21 The other stacked die applications may include, for example, dynamic random-access memory (DRAM), flash stack die, or flip chip ), and wherein the semiconductor device assembly further comprises: a controller communicatively coupled to the semiconductor die via the substrate ) via the substrate ( Col. 34 line 66 – Col. 35 line 2 In some embodiments, some or all of these components are fabricated on a single SoC die or coupled to a single support structure, e.g., to a single carrier substrate ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Sharma (‘060) with Yamazaki (‘974) to implement the semiconductor die is a non-volatile memory semiconductor die or a volatile memory semiconductor die, and wherein the semiconductor device assembly further comprises: a controller communicatively coupled to the semiconductor die via the substrate because this approach creates functional, high-performance, and reliable storage or computing systems.
Claims 11-14 are rejected under U.S.C. 103 as being unpatentable over Yamazaki et al.; US 2022/0131010 A1; 02/2020 in view of Yuda et al.; US 2024/0074170 A1; 08/2022
Claim 11: Yamazaki (‘010) discloses a substrate ( Fig. 11B: substrate ) assembly, comprising: a top insulator layer ( Fig. 11B: insulating layer 368 ); a conductive layer ( Fig. 11B: conductive layer 362 ) below the top insulator layer ( as shown in Fig. 11B ) and comprising: an end of a conductive structure ( Fig. 11B #362 ); a bottom insulator layer ( Fig. 11B: insulating layer 360 ) below the conductive layer ( Fig. 11B #362 );
Yamazaki ( ‘010 ) does not appear to disclose a protective fill structure adjacent to the end of the conductive structure and passing at least partially through the top insulator layer to the bottom insulator layer.
However, Yuda teaches a protective fill structure ( Fig. 8F #58 ) adjacent to the end of the conductive structure ( Fig. 8F #54 ) and passing at least partially through the top insulator layer to the bottom insulator layer ( as shown in Fig. 8F #58 passes through #32 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yuda with Yamazaki (‘010) to implement a protective fill structure adjacent to the end of the conductive structure and passing at least partially through the top insulator layer to the bottom insulator layer because this approach would enhance the mechanical, thermal, and electrical reliability of the assembly.
Claim 12: Yamazaki (‘010) discloses the substrate assembly of claim 11 ( as discussed above ).
Yamazaki (‘010) does not appear to disclose the protective fill structure passes entirely through the top insulator layer.
However, Yuda teaches the protective fill structure ( Fig. 8F #58 ) passes entirely through the top insulator layer ( as shown in Fig. 8F #58 passes through the upper layers of #32 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yuda with Yamazaki (‘010) to implement the protective fill structure passes entirely through the top insulator layer because this approach enables high-density vertical electrical interconnections and ensures structural integrity.
Claim 13: Yamazaki (‘010) and Yuda disclose the substrate assembly of claim 11 ( as discussed above).
Yamazaki (‘010) teaches the conductive structure is a first conductive structure ( Fig. 11B: conductive layer 362 ), the end of the conductive structure is a first end of the first conductive structure ( left side of Fig. 11B #362 ), and wherein the conductive layer ( Fig. 11B: 362 ) below the top insulator layer ( Fig. 11B #368 ) further comprises: a second end of a second conductive structure ( right side of Fig. 11B #362 ), and wherein the protective fill structure ( Fig. 11B: insulating layer 366 ) is between the first end of the first conductive structure and the second end of the second conductive structure ( as shown in Fig. 11B ).
Claim 14: Yamazaki (‘010) and Yuda disclose the substrate assembly of claim 13 ( as discussed above).
Yamazaki (‘010) teaches the protective fill structure ( Fig. 11B #366 ) is configured to electrically isolate the first end of the first conductive structure and the second end of the second conductive structure ( an insulating layer inherently isolates structures ).
Claims 15-17 are rejected under U.S.C. 103 as being unpatentable over Yamazaki et al.; US 2022/0131010 A1; 02/2020 in view of Yuda et al.; US 2024/0074170 A1; 08/2022 as it relates to claim 11 above and further in view of Sharma et al.; US 2024/0222272 A1; 12/2022
Claim 15: Yamazaki (‘010) and Yuda disclose the substrate assembly of claim 11 ( as discussed above ).
Neither Yamazaki (‘010) nor Yuda appear to disclose a solder resist layer above the top insulator layer, and wherein the protective fill structure passes at least partially through the solder resist layer.
However, Sharma (‘272) teaches a solder resist layer ( Fig. 9: solder resist 913 ) above the top insulator layer ( Fig. 9: dielectric layers 909 ), and wherein the protective fill structure ( Fig. 9: underfill material 940 ) passes at least partially through the solder resist layer ( as shown in Fig. 9 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Sharma (‘272) with Yamazaki (‘010) and Yuda to implement a solder resist layer above the top insulator layer, and wherein the protective fill structure passes at least partially through the solder resist layer because this approach would enhance the reliability and precision of the soldering process during assembly.
Claim 16: Yamazaki (‘010), Yuda and Sharma (‘272) disclose the substrate assembly of claim 15 ( as discussed above ).
Neither Yamazaki (‘010) nor Yuda appear to disclose the protective fill structure passes entirely through the solder resist layer.
However, Sharma (‘272) teaches the protective fill structure ( Fig. 9 #940 ) passes entirely through ( as shown in Fig. 9 ) the solder resist layer ( Fig. 9 #913 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Sharma (‘272) with Yamazaki (‘010) and Yuda to implement the protective fill structure passes entirely through the solder resist layer because this approach would maximize mechanical coupling, thermal management and reliability.
Claim 17: Yamazaki (‘010) and Yuda disclose the substrate assembly of claim 11 ( as discussed above).
Neither Yamazaki (‘010) nor Yuda appear to disclose the protective fill structure is configured to satisfy a rigidity threshold of the substrate assembly.
However, Sharma (‘272) teaches the protective fill structure ( Fig. 9 #940 ) is configured to satisfy a rigidity threshold of the substrate assembly ( underfill inherently provides rigidity in substrate assemblies ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Sharma (‘272) with Yamazaki (‘010) and Yuda to implement the protective fill structure is configured to satisfy a rigidity threshold of the substrate assembly because this threshold is primarily used to manage thermos-mechanical stress, prevent solder joint fatigue and minimize package warpage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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