Prosecution Insights
Last updated: August 17, 2026
Application No. 18/497,585

METHODS AND STRUCTURES FOR LOW TEMPERATURE HYBRID BONDING

Final Rejection §103§112
Filed
Oct 30, 2023
Priority
Jun 30, 2023 — provisional 63/511,442
Examiner
ADHIKARI DAWADI, BIPANA
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Adeia Technologies Inc.
OA Round
2 (Final)
100%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
8 granted / 8 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
33 currently pending
Career history
56
Total Applications
across all art units

Statute-Specific Performance

§103
49.5%
+9.5% vs TC avg
§102
11.0%
-29.0% vs TC avg
§112
38.5%
-1.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 8 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Regarding claim 6 objection, applicant amendment has been fully considered. The amendment overcomes the objection; hence the objection is withdrawn for claim 6. Regarding claim 6 rejected under 35 U.S.C. 112(b), applicant amendment has been fully considered. The amendment overcomes the 35 U.S.C. 112(b) rejections, hence 35 U.S.C. 112(b) rejection is withdrawn for claim 6. Applicant’s arguments with respect to claims 1, 29 and 53 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The office now relies upon Liu’538 (US 8802538 B1) which teaches the amended limitation of independent claims 1, 29 and 53 “wherein providing the metal oxide layer over the conductive feature comprises oxidizing a layer of the conductive feature by way of plasma oxidation, thermal oxidation or wet oxidation”. Further, Applicant argument that Liu, Huang and Chen treat metal oxide as an undesirable material to be removed does not distinguish the claimed processes. Claims 1 and 29 expressly require chemically reducing the intentionally formed metal oxide layer back to a metal layer, and claim 53 similarly requires converting the oxide layer back to a metal layer. Accordingly, the claims themselves use the metal oxide as an intermediate process layer rather than as a material retained in the completed hybrid bond. Accordingly, Applicant’s arguments do not overcome the rejections of amended claims 1, 29 and 53. Hence, the rejection for claims 1-8, 11-13, 22, 29-30, 33, 53-54, 67-71 is maintained. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3-6, 22, 29, 33, 67-68, 71 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (CN 113745095 A) in view of Huang (US 20140263586 A1) further in view of Liu’538 (US 8802538 B1). Re: Independent Claim 1 (Currently amended), Liu discloses a process for preparing a first element for hybrid bonding, the process comprising: providing a metal oxide layer over a conductive feature, wherein the conductive feature is at least partially embedded in a dielectric material (Liu teaches, in Fig. 1 and description of Embodiment 1, a first silicon-oxygen-containing insulating layer 11 (silicon dioxide insulating layer), a first bonding copper pad 12, and a copper oxide thin layer 13 on the surface of the first bonding copper pad 12. Liu further teaches that the mixed bonding structure comprises the first bonding copper pad 12 and insulating layer 11, and that the first bonding copper pad 12 is embedded on the surface of the first silicon-oxygen-containing insulating layer 11, with the insulating layer 11 exposed out of the pad. Liu also states that the first interconnection structure includes a first dielectric layer and a first metal interconnection structure embedded in that dielectric layer and electrically connected to the first bonding copper pad 12. Thus, Liu teaches a metal oxide layer 13 over a conductive feature 12, with the conductive feature at least partially embedded relative to dielectric material); chemically reducing the metal oxide layer to form a metal layer (Liu teaches in Step S12 and Fig. 1, that mixed gas of hydrogen and nitrogen is excited into plasma, and that the copper oxide thin layer 13 is reduced by plasma bombardment to reduce the copper oxide to copper. Liu further states that the copper oxide thin layer 13 on the surface of the first bonding copper pad 12 is reduced into a copper thin layer, thereby improving the flatness and electrical connection after mixed bonding process). Regarding “the conductive feature and the dielectric material forming a bonding layer of the first element”, Liu teaches bonding copper pad 12 and silicon-oxygen-containing insulating layer 11 at the mixed bonding interfaces, but Liu is silent regarding expressly describing those structures as “a bonding layer of the first element”. However, Huang teaches, in Fig. 1 and ¶¶ [0020] - [0022], that surface dielectric layer 110 and metal pads 112 are used for the subsequent bonding, that metal pads 112 are formed in surface dielectric layer 110, and that these structures are part of package component 100 to be bonded to package component 200 shown in Fig. 2, which includes corresponding surface dielectric layer 210 and metal pads 212. Thus, Huang teaches the conductive feature and dielectric material together forming the bonding layer used for bonding of a first element. Regarding “preparing a bonding surface of the bonding layer of the first element for hybrid bonding to a second element”, Liu teaches that the same plasma treatment (step S12) reduces the oxide and breaks silicon-oxygen bonds on the surface of insulating layer 11, and then step S13 and Fig. 2, the treated wafer is removed from the plasma chamber so that surface of insulating layer 11 forms -SiOH group, thereby completing preliminary activation of the mixed bonding interface. Liu is silent regarding expressly describing the later bonding operation i.e., first element being hybrid bonded to a second element after such preparation. However, Huang teaches, in Figs. 1-2 and 8-9, ¶ [0014], package component 100 is surface-treated at surface treatment station 304 in integrated hybrid bonding system 300, cleaned at integrated cleaning station 306, and then, in ¶ [0035], package components 100 and 200 are transferred to pre-bonding station 308 shown in Figs. 8-9, aligned so that bond pads 112 align with bond pads 212, and then pressed together, with substantially no oxide regrown because oxide removal occurred shortly beforehand in integrated cleaning station 306. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the oxide-reduction and interface-activation process of Liu, including reduction of copper oxide thin layer 13 on bonding copper pad 12 adjacent insulating layer 11, in the explicit hybrid-bonding arrangement of Huang using surface dielectric layer 110, metal pads 112, and pre-bonding of first and second package components 100 and 200, in order to prepare the bonding surface of the first element for hybrid bonding to a second element while improving electrical connection and bonding strength (Huang, ¶ [0038]). Liu and Huang are silent regarding wherein providing the metal oxide layer over the conductive feature comprises oxidizing a layer of the conductive feature by way of plasma oxidation, thermal oxidation or wet oxidation. However, Liu’538 teaches wherein providing the metal oxide layer over the conductive feature comprises oxidizing a layer of the conductive feature by way of plasma oxidation, thermal oxidation or wet oxidation (Liu’538 teaches, in Figs. 3A-3B and the column 4 lines 29-44, forming copper oxide layers 209 and 309 by oxidizing exposed surface portions of copper pads 205 and 305 embedded in dielectric layer 207 and 307; and the oxidation may be performed using an O2 plasma process or a thermal oxidation process. Liu’538 teaches controlling the oxidation process to form the coper-oxide layer to a selected depth and thereby facilitate formation of controlled and uniform copper-pad surface profiles for hybrid bonding). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Liu’s copper-oxide thin layer 13 on copper bonding pad 12 using the controlled O2 plasma oxidation or thermal oxidation process taught by Liu’538 before performing Liu’s chemical reduction treatment, in order to provide controlled and repeatable formation of copper-oxide layer and improve uniformity and process control of the copper bonding surface for hybrid bonding. Re: Claim 3 (Original), Liu, Huang and Liu’538 disclose all the limitations of claim 1 on which this claim depends. Liu further teaches wherein the metal oxide layer comprises an oxide of a metal of the conductive feature (Liu teaches, in Step S11 description, that the conductive feature is a bonding copper pad 12 and that the metal oxide layer is a copper oxide thin layer 13 formed in the surface of that bonding copper pad. Thus, Liu teaches that the metal oxide layer comprises an oxide of the same metal of the conductive feature, namely, a copper oxide of the copper bonding pad). Re: Claim 4 (Original), Liu, Huang and Liu’538 disclose all the limitations of claim 1 on which this claim depends. Liu further teaches wherein the metal layer comprises a layer of a metal of the conductive feature (Liu teaches that the conductive feature is a bonding copper pad and 12 and that the oxide on that conductive feature is a copper oxide thin layer 13. Liu further teaches reducing that copper oxide thin layer to copper, and the abstract states that the copper oxide thin layer on the surface of the bonding copper pad is reduced to a copper thin layer. Thus, Liu teaches that the resulting metal layer is a layer of the same metal as the conductive feature, namely, a copper layer on a copper conductive feature). Re: Claim 5 (Original), Liu, Huang and Liu’538 disclose all the limitations of claim 1 on which this claim depends. Liu further teaches wherein the metal layer is more conductive than the metal oxide layer (Liu teaches, in abstract, that the copper oxide thin layer on the bonding copper pad adversely affects the electrical connection after hybrid bonding, and further teaches reducing the copper oxide thin layer to copper so that the copper oxide thin layer on the bonding copper pad surface is reduced to a copper thin layer, thereby avoiding the influence of the copper oxide thin layer on the electrical connection after hybrid bonding and improving product yield. Liu would have made it obvious to a person of ordinary skill in the art that the resulting metal layer is more electrically conductive than the metal oxide layer it replaces, because the stated reason for reducing the oxide to copper is to improve the electrical connection at the bond interface). Re: Claim 6 (Currently amended), Liu, Huang and Liu’538 disclose all the limitations of claim 1 on which this claim depends. Liu further teaches wherein the conductive feature and the metal oxide layer comprise at least one common metal, and the at least one common metal comprises at least one of copper, nickel, gold, indium, molybdenum, cobalt, zinc, tungsten, tantalum, titanium, aluminum, chromium, tin, platinum, silver, ruthenium and palladium (Liu teaches, in Step S11 description, that the conductive feature 12 is a bonding copper pad and that the metal oxide layer 13 is a copper oxide thin layer formed on the surface of that bonding copper pad. Thus, Liu teaches that both the metal of the conductive feature and the metal in the metal oxide layer comprise copper, which is one of the listed metals in claim 6). Re: Claim 22 (Original), Liu, Huang and Liu’538 disclose all the limitations of claim 1 on which this claim depends. Liu further teaches wherein chemically reducing the metal oxide layer comprises exposing the first element to a reducing environment (Liu teaches, in Step S12 description, introducing mixed gas of hydrogen and nitrogen into a plasma activation chamber, exciting the gas to plasma, and reducing the copper oxide thin layer 13 on the first bonding copper pad 12 to copper. Thus, Liu teaches exposing the first element to a reducing environment in order to chemically reduce the metal oxide layer). Re: independent Claim 29 (Currently amended), Liu discloses a process for hybrid bonding, the process comprising: providing a metal oxide layer over a first conductive feature, wherein the first conductive feature is at least partially embedded in a first dielectric material ((Liu teaches, in Fig. 1 and description of Embodiment 1, a first silicon-oxygen-containing insulating layer 11 (silicon dioxide insulating layer), a first bonding copper pad 12, and a copper oxide thin layer 13 on the surface of the first bonding copper pad 12. Liu further teaches that the mixed bonding structure comprises the first bonding copper pad 12 and insulating layer 11, and that the first bonding copper pad 12 is embedded on the surface of the first silicon-oxygen-containing insulating layer 11, with the insulating layer 11 exposed out of the pad. Liu also states that the first interconnection structure includes a first dielectric layer and a first metal interconnection structure embedded in that dielectric layer and electrically connected to the first bonding copper pad 12. Thus, Liu teaches a metal oxide layer 13 over a conductive feature 12, with the conductive feature at least partially embedded relative to dielectric material),; chemically reducing the metal oxide layer to form a metal layer (Liu teaches in Step S12 and Fig. 1, that mixed gas of hydrogen and nitrogen is excited into plasma, and that the copper oxide thin layer 13 is reduced by plasma bombardment to reduce the copper oxide to copper. Liu further states that the copper oxide thin layer 13 on the surface of the first bonding copper pad 12 is reduced into a copper thin layer, thereby improving the flatness and electrical connection after mixed bonding process). Regarding “the first conductive feature and the first dielectric material forming a first bonding layer of a first element”, Liu teaches bonding copper pad 12 and silicon-oxygen-containing insulating layer 11 at the mixed bonding interfaces, but Liu is silent regarding expressly describing those structures as “a bonding layer of the first element”. However, Huang teaches, in Fig. 1 and ¶¶ [0020] - [0022], that surface dielectric layer 110 and metal pads 112 are used for the subsequent bonding, that metal pads 112 are formed in surface dielectric layer 110, and that these structures are part of package component 100 to be bonded to package component 200 shown in Fig. 2, which includes corresponding surface dielectric layer 210 and metal pads 212. Thus, Huang teaches the conductive feature and dielectric material together forming the bonding layer used for bonding of a first element. Regarding “preparing a first bonding surface of the first bonding layer of the first element for hybrid bonding”, Liu teaches that the same plasma treatment (step S12) reduces the oxide and breaks silicon-oxygen bonds on the surface of insulating layer 11, and then step S13 and Fig. 2, the treated wafer is removed from the plasma chamber so that surface of insulating layer 11 forms -SiOH group, thereby completing preliminary activation of the mixed bonding interface. Liu is silent regarding expressly describing the later bonding operation i.e., first element being hybrid bonded to a second element after such preparation. However, Huang teaches, in Figs. 1-2 and 8-9, ¶ [0014], package component 100 is surface-treated at surface treatment station 304 in integrated hybrid bonding system 300, cleaned at integrated cleaning station 306, where the treated surfaces are the bonding surfaces of surface dielectric layer 110 and metal pads 112 used for subsequent hybrid bonding. Regarding “directly bonding the first dielectric material to a second dielectric material of a second element”, Liu teaches activation of the first silicon-oxygen-containing insulating layer 11, and also teaches, in Embodiment 2, a corresponding second-side structure including a second bonding copper pad and a second silicon-oxygen-containing insulating layer. Liu is silent regarding expressly disclosing the direct bonding step between the first dielectric material and the second dielectric material. However, Huang teaches, in Fig. 2, a second element i.e., package component 200, including surface dielectric layer 210 and metal pads 212. Huang further teaches, in Fig. 8, that package components 100 and 200 are aligned and pressed together in pre-bonding station 308, and that after the pre-bonding, surface dielectric layers 110 and 210 are bonded to each other. This teaches directly bonding the first dielectric material to the second dielectric material of the second element. Liu is further silent regarding “after bonding the first dielectric material to the second dielectric material, annealing the first element and the second element at an annealing temperature to complete a hybrid bond between the first conductive feature of the first element and a second conductive feature of the second element”. However, Huang teaches, in ¶ [0036], that after pre-bonding, the bonded pair 324 is transferred to annealing station 312 and annealed at about 300 degree C to about 400 degree C for about 1 hour to about 2 hours. Huang further teaches, in ¶ [0037], that during annealing, oxide layers 110 and 210 form strong Si-O-Si fusion bonds and the copper in metal pads 112 and 212 diffuse to each other, so that metal-to-metal bonds are formed, and the resulting bonds between package components 100 and 200 are hybrid bonds. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the oxide-reduction and interface-activation process of Liu, including reduction of copper oxide thin layer 13 on first bonding copper pad 12 adjacent first silicon-oxygen-containing insulating layer 11, in the explicit hybrid-bonding workflow of Huang using dielectric layers 110/210, metal pads 112/212, pre-bonding station 308, and annealing station 312, in order to prepare the first bonding surface for hybrid bonding, directly bond opposing dielectric surfaces, and then complete a high-quality hybrid bond with improved electrical connection and bond strength after annealing. Liu teaches that reducing the copper oxide to copper avoids adverse impact on electrical connection after hybrid bonding and improves yield, while Huang teaches the corresponding direct dielectric bonding and post-bond annealing sequence that forms the completed hybrid bond between opposing conductive features. Liu and Huang are silent regarding wherein providing the metal oxide layer over the conductive feature comprises oxidizing a layer of the conductive feature by way of plasma oxidation, thermal oxidation or wet oxidation. However, Liu’538 teaches wherein providing the metal oxide layer over the conductive feature comprises oxidizing a layer of the conductive feature by way of plasma oxidation, thermal oxidation or wet oxidation (Liu’538 teaches, in Figs. 3A-3B and the column 4 lines 29-44, forming copper oxide layers 209 and 309 by oxidizing exposed surface portions of copper pads 205 and 305 embedded in dielectric layer 207 and 307; and the oxidation may be performed using an O2 plasma process or a thermal oxidation process. Liu’538 teaches controlling the oxidation process to form the coper-oxide layer to a selected depth and thereby facilitate formation of controlled and uniform copper-pad surface profiles for hybrid bonding). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Liu’s copper-oxide thin layer 13 on copper bonding pad 12 using the controlled O2 plasma oxidation or thermal oxidation process taught by Liu’538 before performing Liu’s chemical reduction treatment, in order to provide controlled and repeatable formation of copper-oxide layer and improve uniformity and process control of the copper bonding surface for hybrid bonding. Re: Claim 33 (Original), Liu, Huang and Liu’538 disclose all the limitations of claim 29 on which this claim depends. Huang further teaches wherein the first conductive feature and the second conductive feature comprise metal (Huang teaches, in ¶ [0020], metal pads 112 in surface dielectric layer 110 on package component 100 and metal pads 212 in surface dielectric layer 210 on package component 200 and the metal pads are formed of copper, aluminum, nickel, tungsten or alloys thereof). Re: Claim 67 (New), Liu, Huang and Liu’538 disclose all the limitations of claim 22 on which this claim depends. Liu further teaches wherein the reducing environment comprises a hydrogen-containing plasma (Liu teaches, in the description of step S12, introducing a mixed gas of hydrogen and nitrogen into a plasma activation chamber and exciting the mixed gas to form plasma for reducing copper oxide thin layer 13 to copper). Re: Claim 68 (New), Liu, Huang and Liu’538 disclose all the limitations of claim 22 on which this claim depends. Liu further teaches wherein the reducing environment comprises hydrogen gas (Liu teaches, in the description of steps S11 and S12, introducing a mixed gas of hydrogen and nitrogen into a plasma activation chamber and exciting the mixed gas to form plasma for reducing copper oxide thin layer 13 to copper. Liu further teaches that the proportion of hydrogen in the mixed gas is less than 5%. Thus, the reducing environment comprises hydrogen gas). Re: Claim 71 (New), Liu, Huang and Liu’538 disclose all the limitations of claim 1 on which this claim depends. Liu’538 further teach wherein oxidizing the layer comprises plasma oxidation (Liu’538 teaches, in Figs. 3A-3B and the column 4 lines 29-44, forming copper oxide layers 209 and 309 by oxidizing exposed surface portions of copper pads 205 and 305 embedded in dielectric layer 207 and 307; and the oxidation may be performed using an O2 plasma oxidation process. Thus Liu’538 teaches oxidizing the layer of conductive feature by plasma oxidation). Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Liu (CN 113745095 A) in view of Huang (US 20140263586 A1) further in view of Liu’538 (US 8802538 B1) and further in view of Fang (CN 104233433 B). Re: Claim 2 (Original), Liu, Huang and Liu’538 disclose all the limitations of claim 1 on which this claim depends. Liu, Huang and Liu538 are silent regarding wherein the metal oxide layer comprises metal oxide grains. However, Fang teaches wherein the metal oxide layer comprises metal oxide grains (Although Liu teaches the claimed metal oxide layer in the form of the copper oxide thin layer 13 on the first bonding copper pad 12, Liu does not expressly describe the oxide layer in terms of grains. Fang expressly teaches that a cuprous oxide (Cu2O) thin film has a nanocrystalline structure and a grain size of 100-150nm). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide or recognize the copper oxide thin layer 13 of Liu as having a known grain-containing copper-oxide thin film microstructure as taught by Fang, in order to employ a known and controllable oxide-film morphology for the copper oxide layer formed on the bonding copper pad surface. Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (CN 113745095 A) in view of Huang (US 20140263586 A1) further in view of Liu’538 (US 8802538 B1) and further in view of Huang’347 (US 20230411347 A1). Re: Claim 7 (Original), Liu, Huang and Liu’538 disclose all the limitations of claim 1 on which this claim depends. Liu, Huang and Liu’538 are silent regarding wherein the metal layer comprises nanograins. However, Huang’347 teaches wherein the metal layer comprises nanograins (Huang’347 teaches, in ¶¶ [0022]-[0025] in Cu-Cu bonding process for semiconductor packaging, that at least one bonding surface has a nanograins of copper and states that Cu samples fabrication by electrodeposition with a top layer consisting of nano-sized grains can be directly compressed at 100-250 °C to achieve good Cu-Cu direct welding). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the reduced copper layer of Liu in view of Huang and Liu’538 as a nanograin-containing copper layer as taught by Huang’347 on order to improve low-temperature copper-to-copper bonding performance, promote good interface grain growth, and obtain strong bonding at reduced temperature and stress (Huang’347 ¶ [0018]). Re: Claim 8 (Original), Liu, Huang, Liu’538 and Huang’347 disclose all the limitations of claim 7 on which this claim depends. Huang’347 further teaches wherein the nanograins have an average dimension in the range of about 2 nm to 100 nm (Huang’347 teaches, in ¶ [0023], nanograins of copper have average grain size of 5nm to 500nm, 10 nm to 250nm and specifically 15nm to 100nm). Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (CN 113745095 A) in view of Huang (US 20140263586 A1) further in view of Liu’538 (US 8802538 B1) and further in view of Uzoh (US 20200051937 A1). Re: Claim 11 (Original), Liu, Huang and Liu’538 disclose all the limitations of claim 1 on which this claim depends. Both Liu, Huang and Liu’538 are silent regarding further comprising, before providing the metal oxide layer over the conductive feature, forming a recess in the conductive feature relative to an upper surface of the bonding layer. However, Uzoh teaches further comprising, before providing the metal oxide layer over the conductive feature, forming a recess in the conductive feature relative to an upper surface of the bonding layer (Uzoh teaches, in ¶ [0031], a bonding surface 108 of insulating layer 106 having embedded conductive features 110, where the bonding surface is planarized to meet dielectric roughness and metallic recess specifications for direct bonding. Uzoh further teaches, in ¶ [0032], that planarization can produce recess 112 in the exposed surface of metal features 110, and also teaches that the exposed surface of the conductive features 110 may be intentionally recessed, and teaches, in ¶ [0060], that portions of conductive features 110 may be selectively partially removed with respect to the bonding surface of dielectric 106 to a predetermined depth by etching). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the Liu/Huang/Liu’538 process so that the conductive feature, such as first bonding copper pad 12 of Liu/ metal pad 112 of Huang, is first formed with a recess relative to the upper surface of the bonding layer, and only thereafter provided with the oxide layer of the claim 1 process, in order to provide room for material expansion during subsequent bonding and possible annealing while maintaining a suitable direct/hybrid bonding surface profile (Uzon, ¶ [0031]). Re: Claim 12 (Original), Liu, Huang, Liu’538 and Uzoh disclose all the limitations of claim 11 on which this claim depends. Uzoh further teaches wherein a depth of the recess is in the range of about 1 nm to 100 nm relative to the upper surface (Uzoh teaches, in ¶ [0061], that predetermined recesses 112 can have depth d1 of 50nm to 500nm relative to the upper surface, which overlaps the claimed range). Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Liu (CN 113745095 A) in view of Huang (US 20140263586 A1) further in view of Liu’538 (US 8802538 B1) and further in view of Chen (US 20150031189 A1). Re: Claim 13 (Original), Liu, Huang and Liu’538 disclose all the limitations of claim 1 on which this claim depends. Liu, Huang and Liu’538 are silent regarding wherein providing the metal oxide layer over the conductive feature comprises oxidizing a conductive material disposed over the dielectric material and oxidizing a part of the conductive feature. However, Chen teaches wherein providing the metal oxide layer over the conductive feature comprises oxidizing a conductive material disposed over the dielectric material and oxidizing a part of the conductive feature (Chen teaches, in Figs. 3C-3D and ¶ [0025], a semiconductor wafer 100 having conductive pad 112 embedded in and surrounded by insulating material 114, with metal oxide layer 115 formed on the top surface of conductive pad 112 after CMP process 10. Chen further teaches, in ¶ [0026], that the wafer surface is then subjected to plasma process 20, and expressly states that metal oxide is formed on a surface of the conductive structure. It also teaches that when hydrogen is used in plasma process 20, a portion of metal oxide layer 115 is converted to metal, while some metal oxide 115 still remains on conductive pad 112. Thus, Chen teaches providing the oxide layer by oxidizing the exposed conductive material at the dielectric bonding surface and oxidizing part of the conductive feature itself). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the oxide layer in the Liu/Huang process using the oxide-formation approach taught by Chen, in order to form the desired metal oxide on the exposed bonding-feature surface in a hybrid-bonding surface-preparation flow before the later reduction step. Liu already teaches a copper oxide thin layer 13 on first bonding copper pad 12 that is subsequently reduced to copper for improved bonding yield, Huang supplies the hybrid-bonding framework using surface dielectric layer 110 and metal pads 112, and Chen teaches that, in a hybrid-bonding process, a wafer having conductive pad 112 in insulating material 114 is plasma treated such that metal oxide is formed on the surface of the conductive structure. Using that known oxide-formation technique in the Liu/Huang process would have been predictable implementation choice. Claim 30 and 69 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (CN 113745095 A) in view of Huang (US 20140263586 A1) further in view of Liu’538 (US 8802538 B1) and further in view of Uzoh’396 (US 20200194396 A1). Re: Claim 30 (Original), Liu, Huang and Liu’538 disclose all the limitations of claim 29 on which this claim depends. Liu, Huang and Liu’538 are silent regarding wherein the first conductive feature comprises copper, and wherein the annealing temperature is below about 250°C. However, Uzoh’396 teaches wherein the first conductive feature comprises copper, and wherein the annealing temperature is below about 250°C (Uzoh’396 teaches that dies and/or wafers having copper conductive features 110 at bonding surface 108 are directly hybrid bonded at a reduced temperature, and expressly teaches bonding the conductive features together using a low temperature less than 200°C, while also teaching lower temperature hybrid bonding below 220°C). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use a post-bond annealing temperature below about 250°C in the Liu/Huang hybrid-bonding process in order to complete the copper-to-copper hybrid bond while reducing thermal budget and other temperature related bonding challenges (Uzoh’396 ¶ [0034]). Re: Claim 69 (New), Liu, Huang, Liu’538 and Uzoh’396 disclose all the limitations of claim 30 on which this claim depends. Uzoh’396 further teaches wherein the annealing temperature is below about 200°C (Uzoh’396 teaches, in ¶ [0049], that dies and/or wafers having copper conductive features 110 at bonding surface 108 are directly hybrid bonded at a reduced temperature, and expressly teaches bonding the conductive features together using a low temperature less than 200°C (e.g., 80 to 180 degrees C)). Claim 53, 70 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20140263586 A1) in view of Chen (US 20150031189 A1) further in view of Liu’538 (US 8802538 B1). Re: Independent Claim 53 (Currently amended), Huang discloses a method of fabricating a device, the method comprising: providing the device having a base substrate and a hybrid bonding layer disposed over the base substrate, the hybrid bonding layer having at least one conductive feature at least partially embedded in a dielectric material, the at least one conductive feature being exposed at an upper surface (Huang teaches, in Fig 1 and ¶¶ [0020] – [0021], a device including substrate 102, surface dielectric layer 110, and metal pads 112. Huang expressly teaches that surface dielectric layer 110 and metal pads 112 are used for subsequent bonding, and that the top surface of surface dielectric layer 110 and the top surfaces of metal pads 112 are substantially level with each other, so that the conductive features are exposed at the upper surface of the bonding layer. Huang further teaches that metal pads 112 are formed in surface dielectric layer 110, thereby teaching conductive features at least partially embedded in dielectric material). Regarding “converting a top layer of the at least one conductive feature to an oxidized layer”, Huang teaches metal oxide regions 114 formed on the surfaces of metal pads 112, and teaches that these oxide regions may be native oxide regions formed due to exposure of the pads to air. Huang is silent regarding expressly describing this as a process step of converting a top layer of the at least one conductive feature to an oxidized layer. However, Chen teaches a semiconductor wafer having conductive pad 112 embedded in insulating material 114, and teaches that after CMP process 10, a metal oxide layer 115 is formed on the surface of conductive pad 112, where the oxide may be copper oxide. Thus, Chen teaches converting a surface layer of the conductive feature to an oxidized layer. Regarding, converting the oxidized layer to a metal layer, Huang teaches that hydrogen in the plasma treatment helps reduce the metal oxide 114 on the surfaces of metal pads 112 back to metal. Huang is silent regarding expressly teaching the more specific conversion of the oxidized layer itself as a distinct top layer conversion step. However, Chen teaches, in ¶ [0026], that when hydrogen is used in plasma process 20, a portion of metal oxide 115 is converted to metal. Thus, the combined teachings disclose converting the oxidized layer to a metal layer. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the explicit oxide-formation and oxide-to metal conversion sequence taught by Chen in the hybrid-bonding layer structure of Huang, in order to prepare the exposed metal bonding features in a known hybrid-bonding fabrication flow while improving bonding readiness of the conductive surface. Huang already teaches the structural framework of substance 102, surface dielectric layer 110, and exposed metal pads 112 used for hybrid bonding, and Chen teaches that, in the same hybrid-bonding context, a metal oxide layer is formed on the conductive pad surface and then at least partially converted back to metal during treatment. Combining these teachings would have been a predictable use if know surface-treatment techniques for their known purpose. Huang and Chen are silent regarding wherein providing the metal oxide layer over the conductive feature comprises oxidizing a layer of the conductive feature by way of plasma oxidation, thermal oxidation or wet oxidation. However, Liu’538 teaches wherein providing the metal oxide layer over the conductive feature comprises oxidizing a layer of the conductive feature by way of plasma oxidation, thermal oxidation or wet oxidation (Liu’538 teaches, in Figs. 3A-3B and the column 4 lines 29-44, forming copper oxide layers 209 and 309 by oxidizing exposed surface portions of copper pads 205 and 305 embedded in dielectric layer 207 and 307; and the oxidation may be performed using an O2 plasma process or a thermal oxidation process. Liu’538 teaches controlling the oxidation process to form the coper-oxide layer to a selected depth and thereby facilitate formation of controlled and uniform copper-pad surface profiles for hybrid bonding). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the metal oxide layer on the exposed conductive pad of Huang-Chen hybrid-bonding structure using the controlled O2 plasma oxidation or thermal oxidation process taught by Liu’538, in order to provide controlled and repeatable formation of copper-oxide layer and improve uniformity and process control of the copper bonding surface for hybrid bonding. Re: Claim 70 (New), Huang, Chen and Lin’538 disclose all the limitations of claim 53 on which this claim depends. Chen further teaches wherein the base substrate comprises single crystal semiconductor material (Chen teaches, in ¶ [0011], that semiconductor wafer 100 includes semiconductor substrate 102 which is made of silicon or other semiconductor material and that substrate 102 may include silicon oxide over single-crystal silicon. Thus, Chen teaches a base substrate comprising single crystal semiconductor material). Claim 54 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20140263586 A1) in view of Chen (US 20150031189 A1) further in view of Liu’538 (US 8802538 B1) and further in view of Huang’347 (US 20230411347 A1). Re: Claim 54 (Original), Huang, Chen and Lin’538 disclose all the limitations of claim 53 on which this claim depends. Huang, Chen and Liu’538 are silent regarding wherein the metal layer comprises nanograins. However, Huang’347 teaches wherein the metal layer comprises nanograins (Huang’347 teaches, in ¶¶ [0022]-[0025] in Cu-Cu bonding process for semiconductor packaging, that at least one bonding surface has a nanograins of copper and states that Cu samples fabrication by electrodeposition with a top layer consisting of nano-sized grains can be directly compressed at 100-250 °C to achieve good Cu-Cu direct welding). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the metal layer formed by Huang/Chen/Liu’538 process as a nanograin-containing copper layer as taught by Huang’347 on order to improve low-temperature copper-to-copper bonding performance, promote good interface grain growth, and obtain strong bonding at reduced temperature and stress (Huang’347 ¶ [0018]). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
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Prosecution Timeline

Oct 30, 2023
Application Filed
Apr 21, 2026
Non-Final Rejection mailed — §103, §112
Jun 18, 2026
Response Filed
Aug 06, 2026
Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 4 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
3y 3m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 8 resolved cases by this examiner. Grant probability derived from career allowance rate.

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