DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed on 16 March 2026, with respect to the rejections of claims 1, 11, and 17 under 35 U.S.C. § 102 and/or 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Kim ‘441 (US 2020/0075441 A1). Please see the 35 U.S.C. § 103 rejections of claims 1, 11, and 17 below.
In summary, this application is not placed in a condition for an allowance.
Claim Objections
Claim 20 is objected to because of the following informalities: a typographical error is found: a second insulating layer between the second semiconductor die stack [sic: and] an additional passive electronic component [sic: that is] disposed entirely on the second insulating layer.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5, 11-12 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2020/0294889 A1) in view of Kim ‘441 (US 2020/0075441 A1) as evidenced by Kim ‘040 (US 2021/0091040 A1).
Regarding claim 1, Choi semiconductor device assembly (Fig. 4: 10S, Fig. 6: 20S), comprising:
a substrate (Fig. 4: 600; alternatively, Fig. 6: 2600);
a semiconductor die (Fig. 4: 210T and/or 210B; alternatively, Fig 6: 2210T and/or 2210B; ¶ [0024]: 210 is comprised of a semiconductor material) disposed on the substrate;
a passive electronic component (Fig. 4: 230T and/or 230B; alternatively, Fig. 6: 2230T and/or 2230B; note: ¶ [0034] teaches 230 to include 231, 232 and 233) disposed on the semiconductor die; and
an insulating layer between the semiconductor die and the passive electronic component (¶ [0039]: “an insulation layer (not shown in FIG. 3) may be disposed between the first capacitor electrode 231 and the second surface 202 of the first bridge die body 210 such that the first capacitor electrode 231 is electrically insulated from the first bridge die body 210”), wherein the insulating layer is disposed on a surface (Fig. 4: top surface of 210T and/or 210B; Fig. 6: top surface of 2210T and/or 2210B) of the semiconductor die and the passive electronic component is disposed on the insulating layer (as explained in ¶ [0039], the insulating layer is disposed between capacitor electrode 231 and bridge die body 210 ).
Choi further teaches the passive electronic component to be a capacitor comprising of a first electrode (231), a dielectric (233), and a second electrode (232), with both electrodes connected to the semiconductor die (see Fig. 1). Hence, Choi does not explicit teach the passive electronic component is disposed entirely on the insulating layer.
Kim ‘441, in the same field of invention, teaches a passive electronic component (208, see Fig. 2A; ¶ [0018]: “Arrays of passive devices such as resistors or capacitors can also be formed as a semiconductor device, even when the device has no active devices”; hence die 208 is a passive component ) being disposed entirely on the insulating layer (222 is a die attach film; as evidenced by Kim ‘040, ¶ [0025], die attach film is an insulating layer).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Choi to dispose the passive electronic component entirely on the insulating layer. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for at least the purpose of substituting the first electrode and second electrode with a first bond pad (left 210, see Kim ‘441 Fig. 2) and a second bond pad (right 210), for the further purpose of connecting the passive electronic component to another device component (214, 215) other than the semiconductor die (212 is analogous to the semiconductor die of Choi since it is disposed under the passive electronic component) through the use of wire bonds (218) and for the further purpose of using the insulating film as an adhesive (as evidenced by Kim ‘040, ¶ [0025], die attach films are adhesives).
Regarding claim 2, the semiconductor device assembly of claim 1, wherein the passive electronic component is a resistor, an inductor, or a capacitor (Choi ¶ [0039] : 230 is a capacitor).
Regarding claim 3, the semiconductor device assembly of claim 1, wherein the insulating layer is a die attach film (Kim ‘441 ¶0024] )
Regarding claim 5, the semiconductor device assembly of claim 1, wherein the surface (top surfaces of 210T/210B or 2230T/2230B ) of the semiconductor die is facing the passive electronic component, and is configured to be electrically inactive (Fig. 2A of Kim ‘441 teaches the bottom of the passive electronic component not having any electrical connection; this interpretation aligns with the definition of electrically inactive as found in ¶ [0038] of the instant application), and
wherein the semiconductor die is electrically connected to the substrate in a direct chip attachment configuration (Kim ‘441 Fig. 2A teaches 208 attached to 212 in a flip chip configuration; note: ¶ [0032] of the instant application defines “direct chip configuration” as a flip chip bonding configuration).
Regarding claim 11, Choi teaches a semiconductor package (Fig. 4: 10S; alternatively, Fig. 6: 20S), comprising:
a substrate (Fig. 4: 600; alternatively, Fig. 6: 2600);
a semiconductor die (Fig. 4: 210T and/or 210B; alternatively, Fig 6: 2210T and/or 2210B) disposed on the substrate; and
an insulating layer disposed on the semiconductor die (¶ [0039]: “an insulation layer (not shown in FIG. 3) may be disposed between the first capacitor electrode 231 and the second surface 202 of the first bridge die body 210 such that the first capacitor electrode 231 is electrically insulated from the first bridge die body 210”); and
a passive electronic component (Fig. 4: 230T and/or 230B; alternatively, Fig. 6: 2230T and/or 2230B) disposed on the insulating layer (see ¶ [0039] ).
Choi further teaches the passive electronic component to be a capacitor comprising of a first electrode (231), a dielectric (233), and a second electrode (232), with both electrodes connected to the semiconductor die (see Fig. 1). Hence, Choi does not explicit teach the passive electronic component is disposed entirely on the insulating layer.
Kim ‘441, in the same field of invention, teaches a passive electronic component (208, see Fig. 2A; ¶ [0018]: “Arrays of passive devices such as resistors or capacitors can also be formed as a semiconductor device, even when the device has no active devices”; hence die 208 is a passive component ) being disposed entirely on the insulating layer (222 is a die attach film; as evidenced by Kim ‘040, ¶ [0025], die attach film is an insulating layer).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Choi to dispose the passive electronic component entirely on the insulating layer. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for at least the purpose of substituting the first electrode and second electrode with a first bond pad (left 210, see Kim ‘441 Fig. 2) and a second bond pad (right 210), for the further purpose of connecting the passive electronic component to another device component (214, 215) other than the semiconductor die (212 is analogous to the semiconductor die of Choi since it is disposed under the passive electronic component) through the use of wire bonds (218) and for the further purpose of using the insulating film as an adhesive (as evidenced by Kim ‘040, ¶ [0025], die attach films are adhesives).
Regarding claim 12, the semiconductor package of claim 11, wherein the passive electronic component is a resistor, an inductor, or a capacitor (230T, 230B, 2230T, 2230B are all capacitors; see Choi ¶ [0048], [0050] [0062], [0064]).
Regarding claim 14, the semiconductor package of claim 11, further comprising: a casing (Choi Fig. 4: 430; Fig. 6: 2430) that surrounds the semiconductor die.
Regarding claim 15, the semiconductor package of claim 14, wherein the passive electronic component is entirely within the casing (Choi Figs. 4 and 6 show all the above-mentioned capacitors are encapsulated within casing 430 and/or 2430).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2020/0294889 A1) in view of Kim ‘441 (US 2020/0075441 A1) as applied to claim 11 above, and further in view of Zou (US 2021/0151549 A1).
Regarding claim 13, Choi et al. teach the semiconductor package of claim 11, but do not teach wherein the passive electronic is one of a plurality of passive electronic components on the semiconductor die.
Zou, in the same field of invention, teaches a passive electronic component (218) being one of a plurality (more than one 218 is found on top of 220 as shown in Fig. 3A) of passive electronic components disposed on the semiconductor die (220, see ¶ [0037] and Fig. 3A).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zou into the device of Choi et al. to dispose more than one passive electronic component on the semiconductor die. The ordinary artisan would have been motivated to modify Choi et al. in the manner set forth above for at least the purpose of improving the device density (Zou ¶ [0004]) and integration of power management related circuits (¶ [0037]), the quality of the power provided (¶ [0041]), and the over-all device performance (¶ [0003]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2020/0294889 A1) in view of Kim ‘441 (US 2020/0075441 A1) as applied to claim 14 above, and further in view of Liou (US 2011/0169163 A1).
Regarding claim 16, Choi et al. teach the semiconductor package of claim 14, but fails to teach: wherein at least a portion of the passive electronic component is outside of the casing.
Liou, in the same field of invention, teaches a semiconductor package (Figs. 1-4) wherein at least a portion (the top surface and vertical sidewalls of 122) of the passive electronic component (122) is outside of the casing (114).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Liou into the device of Choi et al. to have a portion of the passive electronic component to be outside of the casing. The ordinary artisan would have been motivated to modify Choi et al. in the manner set forth above for at least the purpose of reducing cracks and other stresses on a semiconductor die that uses a material more brittle than silicon dioxide due to difference in thermal expansion of the materials (Liou ¶ [0005], [0027]), for the further purpose of improving the device reliability and lifespan.
Claims 1, 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2019/0341366 A1 ) in view of Choi (US 2020/0294889 A1) and Kim ‘441 (US 2020/0075441 A1) as evidenced by Kim ‘040 (US 2021/0091040 A1).
Regarding claim 1, Chen teaches a semiconductor device assembly (100, see Fig. 12), comprising:
a substrate (102);
a semiconductor die (124t) disposed on the substrate.
However, Chen does not teach the semiconductor device assembly comprising:
a passive electronic component disposed on the semiconductor die; and
an insulating layer between the semiconductor die and the passive electronic component.
Choi, in the same field of invention, teaches a semiconductor device assembly (10S, Fig. 4) comprising:
a passive electronic component (230T) disposed on the semiconductor die (200T; ¶ [0049]: 200T is a bridge die comprised of bridge die body 210T; ¶ [0024]: 210 is comprised of semiconductor material); and
an insulating layer between the semiconductor die and the passive electronic component (¶ [0039]: “an insulation layer (not shown in FIG. 3) may be disposed between the first capacitor electrode 231 and the second surface 202 of the first bridge die body 210 such that the first capacitor electrode 231 is electrically insulated from the first bridge die body 210”), wherein the insulating layer is disposed on a surface (Fig. 4: top surface of 210T and/or 210B; Fig. 6: top surface of 2210T and/or 2210B) of the semiconductor die and the passive electronic component is disposed on the insulating layer (as explained in ¶ [0039], the insulating layer is disposed between capacitor electrode 231 and bridge die body 210 ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Choi into the device of Chen to place a passive electronic component on the semiconductor die, with an insulating layer in between the semiconductor die and the passive electronic component. The ordinary artisan would have been motivated to modify Chen in the manner set forth above for at least the purpose of using the capacitor as part of a power distribution circuit (Choi ¶ [0031], Fig. 2) to supply power to dies (100) in a package used for multiple applications such as a mobile terminal or a desktop computer (Choi ¶ [0070]) and for the further purpose of improving the limited planar area of the first capacitor electrode (231, see Choi Fig. 1) in order to increase the capacitance value (Choi ¶ [0041]) and to reduce the inductance and impedance value of the electrical path associated with the power distribution circuit (Choi ¶ [0037]) and to electrically insulate the semiconductor die and the passive electronic component from each other issuing the insulating layer.
Choi further teaches the passive electronic component to be a capacitor comprising of a first electrode (231), a dielectric (233), and a second electrode (232), with both electrodes connected to the semiconductor die (see Fig. 1). Hence, Choi does not explicit teach the passive electronic component is disposed entirely on the insulating layer.
Kim ‘441, in the same field of invention, teaches a passive electronic component (208, see Fig. 2A; ¶ [0018]: “Arrays of passive devices such as resistors or capacitors can also be formed as a semiconductor device, even when the device has no active devices”; hence die 208 is a passive component ) being disposed entirely on the insulating layer (222 is a die attach film; as evidenced by Kim ‘040, ¶ [0025], die attach film is an insulating layer).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Choi to dispose the passive electronic component entirely on the insulating layer. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for at least the purpose of substituting the first electrode and second electrode with a first bond pad (left 210, see Kim ‘441 Fig. 2) and a second bond pad (right 210), for the further purpose of connecting the passive electronic component to another device component (214, 215) other than the semiconductor die (212 is analogous to the semiconductor die of Choi since it is disposed under the passive electronic component) through the use of wire bonds (218) and for the further purpose of using the insulating film as an adhesive (as evidenced by Kim ‘040, ¶ [0025], die attach films are adhesives).
Regarding claim 4, the semiconductor device assembly of claim 1, wherein the surface (top surface of 124t; Chen Fig. 12 shows die bond pads 126 on the top surface of the topmost 124t) of the semiconductor die is facing the passive electronic component (in view of Choi, the top surface of 124t is the surface that faces the passive electronic component) and is configured to be electrically active (as defined in ¶ [0038] of the instant application, electrically active means wire bonds are connected to the top surface of the die; also see Chen ¶ [0038]),
wherein the semiconductor die is electrically connected to the substrate via one or more wire bonds (130 and 132, see Chen Fig. 12).
Regarding claim 6, the semiconductor device assembly of claim 1, wherein the semiconductor die is a topmost semiconductor die of a semiconductor die stack disposed on the substrate (Chen Fig. 12 shows the topmost die 124t of the die stack; in view of Choi, a passive electronic component is on the top surface of this topmost die).
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2019/0341366 A1 ) in view of Choi (US 2020/0294889 A1) and Kim ‘441 (US 2020/0075441 A1) as applied to claim 6 above, and further in view of Chang (US 2022/0320046 A1).
Regarding claim 7, Chen et al. teach the semiconductor device assembly of claim 6, wherein the semiconductor die stack is a first semiconductor die stack (see Chen Abstract and Fig. 12). However, Chen et al. do not teach the device wherein the semiconductor device assembly further comprises a second semiconductor die stack.
Chang, in the same field of invention, teaches a semiconductor device assembly (1000, see Fig. 10) comprising a first semiconductor die stack (850; alternatively, 700), wherein the semiconductor device assembly and further comprises a second semiconductor die stack (700; alternatively, 850).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chang into the device of Chen et al. to add a second semiconductor device stack. The ordinary artisan would have been motivated to modify Chen et al. in the manner set forth above for at least designing a three-dimensional integrated circuit (3DIC) package for the further purpose of the purpose of improving the integration density, speeds, and bandwidth due to the decreased length of interconnects between the stacked dies (Chang ¶ [0003]-[0004]).
Regarding claim 8, the semiconductor device assembly of claim 7, wherein a height (height of 850; see Chang Fig. 10) of the first semiconductor die stack is shorter than a height (height of 700) of the second semiconductor die stack (as shown in Chang Fig. 10, first stack 850 is shorter in height than second stack 700).
Regarding claim 9, the semiconductor device assembly of claim 7, wherein a (height of 700; see alternatives to Chang Fig. 10 reference in claim 7) height of the first semiconductor die stack is taller than a height (height of 850) of the second semiconductor die stack (as shown in Chang Fig. 10, first stack 700 is taller in height than second stack 850).
Regarding claim 10, the semiconductor device assembly of claim 7, further comprising: one or more passive electronic components (112; see Chen Fig. 4 and ¶ [0034]) disposed on the substrate.
Claims 17 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0320046 A1 in view of Choi (US 2020/0294889 A1), Ye (US 2015/0221624 A1), and Kim ‘441 (US 2020/0075441 A1) as evidenced by Kim ‘040 (US 2021/0091040 A1).
Regarding claim 17, Chang teaches a semiconductor device assembly (1000, Fig. 10), comprising:
a substrate (801);
a first semiconductor die stack (850, see ¶ [0102]) disposed on the substrate;
a second semiconductor die stack (700, see ¶ [0101]) disposed on the substrate.
However, Chang does not teach: a first insulating layer disposed on the first semiconductor die stack; and a passive electronic component disposed on the first insulating layer.
Choi, in the same field of invention, teaches
a first insulating layer (¶ [0039]: “an insulation layer (not shown in FIG. 3) may be disposed between the first capacitor electrode 231 and the second surface 202 of the first bridge die body 210 such that the first capacitor electrode 231 is electrically insulated from the first bridge die body 210”) disposed on a first semiconductor die stack (10S; see Fig. 4); and
a passive electronic component (230T) disposed on the first insulating layer (see ¶ [0039] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Choi into the device of Chang to dispose a first insulating layer on the first semiconductor die stack and to dispose a passive electronic component on the first insulating layer. The ordinary artisan would have been motivated to modify Chang in the manner set forth above for at least the purpose of using passive electronic component, i.e., a capacitor, as part of a power distribution circuit (Choi ¶ [0031], Fig. 2) to supply power to dies (100) in a package used in multiple applications such as a mobile terminal or a desktop computer (Choi ¶ [0070]) and for the further purpose of improving the limited planar area of the first capacitor electrode (231, see Choi Fig. 1) in order to increase the capacitance value (Choi ¶ [0041]) and to reduce the inductance and impedance value of the electrical path associated with the power distribution circuit (Choi ¶ [0037]) and for using the first insulating layer for the purpose of providing electrical insulation between the passive electronic component and a semiconductor die (210T, see Fig. 4) that comprises the die stack.
However, Chang in view of Choi does not teach one or more passive electronic components disposed on the substrate.
Ye, in the same field of invention, teaches one or more passive electronic components (112, see Fig. 5) disposed on the substrate (102).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Ye into the device of Chang in view of Choi to add one or more passive electronic components on the substrate. The ordinary artisan would have been motivated to modify Chang in view of Choi in the manner set forth above for at least the purpose of using the passive electronic components together with a controller die (114), which is also disposed on the substrate for the further purpose of reducing the footprint of the device (see Ye’s Abstract and ¶ [0002]).
Choi further teaches the passive electronic component to be a capacitor comprising of a first electrode (231), a dielectric (233), and a second electrode (232), with both electrodes connected to the semiconductor die (see Fig. 1). Hence, Choi does not explicit teach the passive electronic component is disposed entirely on the insulating layer.
Kim ‘441, in the same field of invention, teaches a passive electronic component (208, see Fig. 2A; ¶ [0018]: “Arrays of passive devices such as resistors or capacitors can also be formed as a semiconductor device, even when the device has no active devices”; hence die 208 is a passive component ) being disposed entirely on the insulating layer (222 is a die attach film; as evidenced by Kim ‘040, ¶ [0025], die attach film is an insulating layer).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kim into the device of Choi to dispose the passive electronic component entirely on the insulating layer. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for at least the purpose of substituting the first electrode and second electrode with a first bond pad (left 210, see Kim ‘441 Fig. 2) and a second bond pad (right 210), for the further purpose of connecting the passive electronic component to another device component (214, 215) other than the semiconductor die (212 is analogous to the semiconductor die of Choi since it is disposed under the passive electronic component) through the use of wire bonds (218) and for the further purpose of using the insulating film as an adhesive (as evidenced by Kim ‘040, ¶ [0025], die attach films are adhesives).
Regarding claim 19, the semiconductor device assembly of claim 17, wherein the first semiconductor die stack is a shortest semiconductor die stack of the semiconductor device assembly (as shown in Chang Fig. 10, 850 is the shortest semiconductor stack among the three stacks).
Regarding claim 20, the semiconductor device assembly of claim 17, further comprising:
a second insulating layer between the second semiconductor die stack [sic: and] an additional passive electronic component [sic: that is ] disposed entirely the second insulating layer (Chang teaches a second die stack; since Choi teaches adding a passive component on any die stack, then the second die stack also contains an insulating layer between the second semiconductor die stack and the additional passive component).
Regarding claim 21, the semiconductor device assembly of claim 17, wherein the passive electronic component is a resistor, an inductor, or a capacitor (Choi ¶ [0023] : 230 is a capacitor).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
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