Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-2 and 6-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ji (US Patent No. 9087885) in further view of Yang (US Patent No. 9257413).
Regarding claim 1, Ji teaches a semiconductor die comprising: a substrate having a front-side surface and a back-side surface; an interlayer insulating layer disposed under the front-side surface of the substrate; a horizontal metal interconnection disposed in the interlayer insulating layer; a front-side pad disposed under a lower surface of the interlayer insulating layer; a front-side bump structure disposed under a lower surface of the front-side pad; a through-electrode vertically passing through the substrate; a back-side insulating layer disposed over the back-side surface of the substrate; a first back-side metal plate layer disposed over the back-side insulating layer; a back-side passivation layer disposed over the back-side insulating layer and covering the first back-side metal plate layer; and a back-side bump structure disposed over the through-electrode and the back-side passivation layer (Fig. 2Z and Col. 8, lines 26-29 point to a semiconductor device comprising a substrate 110, a front side interlayer insulator layer 130U, conductive inner wires 142 (horizontal metal interconnection), a front side pad 145, a front side bump 300, a TSV structure 200 (through-electrode), a back side interlayer insulating layer 160, a redistribution layer 400 (first back-side metal plate layer), a back side passivation layer 170, and a back side bump comprising a conductive layer 520 and a capping layer 530).
Ji fails to teach wherein the through-electrode has a protruding portion that vertically passes through the back-side passivation layer and the first back-side metal plate layer, wherein the protruding portion protrudes upward from the back-side surface of the substrate.
Yang teaches wherein the through-electrode has a protruding portion that vertically passes through the back-side passivation layer and the first back-side metal plate layer, wherein the protruding portion protrudes upward from the back-side surface of the substrate (Fig. 2 points to a semiconductor chip comprising protrusion portions 175 of lower through via electrodes 170 (through-electrode) that penetrate a backside passivation layer 150.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Ji and Yang, such that the through-electrode includes a protruding portion in order to create through silicon via (TSV) electrodes that penetrate a semiconductor chip and enable multiple chips to be electrically connected in a single stack package.
Regarding claim 2, Ji teaches a front-side passivation layer disposed under the lower surface of the interlayer insulating layer to expose the lower surface of the front-side pad and surround a side surface of the front-side pad (Fig. 2Z points to a front side passivation layer 150.).
Regarding claim 6, Ji in combination with Yang teaches wherein the first back-side metal plate layer has a through-electrode hole, and wherein the through-electrode passes vertically through the through-electrode hole (Fig. 2Z of Ji points to a redistribution layer 400 (first back-side metal plate layer) and a back side passivation layer 170. Fig. 2 of Yang further points to protrusion portions 175 of lower through via electrodes 170 (through-electrode) that penetrate a backside passivation layer 150.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji and Yang, such that the first back-side metal plate layer has a through-electrode hole in order to allow the through-electrode to extend and penetrate through the outer backside passivation layer, which would enable multiple chips to be electrically connected in a single stack package.
Regarding claim 7, Yang teaches wherein a portion of the back-side insulating layer protrudes to conformally surround the side surface of the protruding portion of the through-electrode (Fig. 2 and Col. 5, lines 19-22 point to a first backside insulation layer 151 which may have a conformal liner shape to cover the sidewalls of the protrusion portions 175 (through-electrode).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji and Yang, such that a portion of the back-side insulating layer conformally surrounds the through-electrode in order to prevent electrical shorting and/or reduce leakage current.
Regarding claim 8, Yang teaches wherein the portion of the back-side insulating layer has substantially a cylindrical shape or substantially a tube shape (Fig. 2 and Col. 5, lines 19-22 point to the first backside insulation layer 151 which may have a conformal liner shape to cover the sidewalls of the protrusion portions 175 (through-electrode).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji and Yang, such that a portion of the back-side insulating layer would have a substantially cylindrical or tube shape in order to conformally surround the through-electrode and by extension prevent electrical shorting and/or reduce leakage current.
Regarding claim 9, Ji in combination with Yang teaches wherein the first back-side metal plate layer includes: a horizontal plate portion disposed between the back-side insulating layer and the back-side passivation layer to have substantially a plate shape (Fig. 2Z of Ji points to the redistribution layer 400 (horizontal plate portion) formed between the back side interlayer insulating layer 160 and the back side passivation layer 170.); and a vertical protruding portion surrounding a side of the back-side insulating layer surrounding the protruding portion of the through-electrode (Fig. 2 of Yang points to a semiconductor chip comprising protrusion portions 175 of lower through via electrodes 170 (through-electrode) that penetrate a backside passivation layer 150 and a first backside insulation layer 151. Col. 5, lines 19-22 of Yang further points to the first backside insulation layer 151 having a conformal liner shape to cover the sidewalls of the protrusion portions 175 (through-electrode). In light of both Ji and Yang, it is considered obvious that a portion of the first back-side metal plate layer would also be shaped accordingly, such that a vertical protruding portion is formed as a result of the via electrodes 170 penetrating through both the backside passivation and backside insulation layers.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji and Yang, such that the first back-side metal plate layer further includes a vertical protruding portion that conformally surrounds the through-electrode in order to allow the through-electrode to extend and penetrate through the outer backside passivation layer, which would enable multiple chips to be electrically connected in a single stack package.
Regarding claim 10, Yang teaches wherein the vertical protruding portion of the first back-side metal plate layer is in contact with the back-side bump structure (Fig. 2 points to both the backside passivation layer 150 and the first backside insulation layer 151 being in contact with the lower backside bumps 180.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji and Yang, such that the vertical protruding portion of the first back-side metal plate layer, which surrounds a corresponding portion of the back-side insulating layer, is in contact with the back-side bump structure in order to establish communication with said structure and/or allow for signal routing.
Regarding claim 11, Ji in combination with Yang teaches wherein the vertical protruding portion of the first back-side metal plate layer has substantially a cylindrical shape or substantially a tube shape (Fig. 2Z of Ji points to the redistribution layer 400 (first back-side metal plate layer). Fig. 2 and Col. 5, lines 19-22 of Yang point to the first backside insulation layer 151 which may have a conformal liner shape to cover the sidewalls of the protrusion portions 175 (through-electrode).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji and Yang, such that the vertical protruding portion of the first back-side metal plate layer would have a substantially cylindrical or tube shape in order to conformally surround the through-electrode and by extension reduce electromagnetic coupling, suppress noise, and/or shield sensitive signals.
Regarding claim 12, Yang teaches a metal pattern disposed between the first back-side metal plate layer and the back-side bump structure, and wherein the metal pattern is vertically aligned with the through-electrode and the back-side bump structure (Fig. 3 points to an alternative embodiment of a semiconductor chip comprising an interconnection structure 131 (first back-side metal plate layer), an interconnection structure 133 (metal pattern), through via electrodes 270 and bumps 290.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji and Yang, such that a metal pattern is formed between the through-electrode and the back-side bump structure in order to create an interconnection structure that balances electrical isolation and communication between the two components.
Regarding claim 13, Yang teaches wherein the metal pattern is disposed over the first back-side metal plate layer and has a protruding shape upward to be in contact with the through-electrode and the back-side bump structure (Fig. 3 points to an alternative embodiment of a semiconductor chip comprising the interconnection structure 133 (metal pattern).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji and Yang, such that the metal pattern includes a protruding shape in order to vertically connect the through-electrode and the back-side bump structure and by extension balance the need of electrical isolation with that of communication between the two components.
Claim(s) 3, 14-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. in further view of Jung (PGPub No. 20190318470).
Regarding claim 3, Jung teaches a dummy front-side bump structure disposed under the front-side passivation layer and a dummy back-side bump structure disposed over the back-side passivation layer, wherein the substrate includes a through-electrode area in which the through-electrodes are disposed and a dummy area in which the through-electrodes are not disposed, and wherein the dummy front-side bump structure and the dummy back-side bump structure are disposed in the dummy area (Fig. 2 points to a semiconductor die 220 (substrate) comprising a central area (through-electrode area) corresponding to TSVs 225 and an outer area (dummy area) corresponding to dummy bumps 267.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji et al. and Jung, such that a dummy front-side bump structure and a dummy back-side bump structure are formed in order to increase the bonding strength and/or improve the physical stability of the semiconductor die stack.
Regarding claim 14, Ji teaches an interlayer insulating layer disposed under an active surface of the substrate; a horizontal metal interconnection disposed in the interlayer insulating layer; a front-side passivation layer disposed under a lower surface of the interlayer insulating layer; a front-side bump structure disposed under a lower surface of the front-side passivation layer in the through-electrode area; a back-side insulating layer disposed over an in-active surface of the substrate; a first back-side metal plate layer disposed over the back-side insulating layer; a back-side passivation layer disposed over the first back-side metal plate layer; and a back-side bump structure disposed over the through-electrode in the through-electrode area (Fig. 2Z and Col. 8, lines 26-29 point to a semiconductor device comprising a substrate 110, a front side interlayer insulator layer 130U, conductive inner wires 142 (horizontal metal interconnection), a front side passivation layer 150, a front side bump 300, a TSV structure 200 (through-electrode), a back side interlayer insulating layer 160, a redistribution layer 400 (first back-side metal plate layer), a back side passivation layer 170, and a back side bump comprising a conductive layer 520 and a capping layer 530).
Ji fails to teach a substrate having a through-electrode area and a dummy area; a dummy front-side bump structure disposed under the lower surface of the front-side passivation layer in the dummy area; a through-electrode vertically passing through the substrate, the back-side insulating layer, the first back-side metal plate layer, and the back-side passivation layer in the through-electrode area; and a dummy back-side bump structure disposed over the back-side passivation layer in the dummy area.
Yang teaches a through-electrode vertically passing through the substrate, the back-side insulating layer, the first back-side metal plate layer, and the back-side passivation layer in the through-electrode area (Fig. 2 points to a semiconductor chip comprising protrusion portions 175 of lower through via electrodes 170 (through-electrode) that penetrate through a lower semiconductor substrate 110, a first backside insulation layer 151, and a backside passivation layer 150.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Ji and Yang, such that the through-electrode vertically passes through the substrate, the back-side insulating layer, the first back-side metal plate layer, and the back-side passivation layer in order to create through silicon via (TSV) electrodes that penetrate a semiconductor chip and enable multiple chips to be electrically connected in a single stack package.
Ji et al. still fails to teach a substrate having a through-electrode area and a dummy area; a dummy front-side bump structure disposed under the lower surface of the front-side passivation layer in the dummy area; and a dummy back-side bump structure disposed over the back-side passivation layer in the dummy area.
Jung teaches a substrate having a through-electrode area and a dummy area; a dummy front-side bump structure disposed under the lower surface of the front-side passivation layer in the dummy area; and a dummy back-side bump structure disposed over the back-side passivation layer in the dummy area (Fig. 2 points to a semiconductor die 220 (substrate) comprising a central area (through-electrode area) corresponding to TSVs 225 and an outer area (dummy area) corresponding to dummy bumps 267.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji et al. and Jung, such that a dummy front-side bump structure and a dummy back-side bump structure are formed in order to increase the bonding strength and/or improve the physical stability of the semiconductor die stack.
Regarding claim 15, Yang teaches wherein the through-electrode has a protruding portion protruding upward from the in-active surface of the substrate (Fig. 2 points to a semiconductor chip comprising protrusion portions 175 of lower through via electrodes 170 (through-electrode) that penetrate a backside passivation layer 150.), and wherein a portion of the back-side insulating layer protrudes to surround a side surface of the protruding portion of the through-electrode (Fig. 2 and Col. 5, lines 19-22 point to a first backside insulation layer 151 which may have a conformal liner shape to cover the sidewalls of the protrusion portions 175 (through-electrode).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji et al. and Yang, such that the through-electrode includes a protruding portion surrounded by a portion of the back-side insulating layer in order to create through silicon via (TSV) electrodes that enable multiple chips to be electrically connected in a single stack package and which are surrounded by insulating material that prevents electrical shorting and/or reduces leakage current.
Regarding claim 16, Ji in combination with Yang teaches wherein the first back-side metal plate layer has a through-electrode hole, and wherein the through-electrode passes vertically through the through-electrode hole (Fig. 2Z of Ji points to a redistribution layer 400 (first back-side metal plate layer) and a back side passivation layer 170. Fig. 2 of Yang further points to protrusion portions 175 of lower through via electrodes 170 (through-electrode) that penetrate a backside passivation layer 150.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji et al. and Yang, such that the first back-side metal plate layer has a through-electrode hole in order to allow the through-electrode to extend and penetrate through the outer backside passivation layer, which would enable multiple chips to be electrically connected in a single stack package.
Regarding claim 18, Ji teaches wherein the first back-side metal plate layer is connected to the back-side bump structure (Fig. 2Z points to the redistribution layer 400 (first back-side metal plate layer) and the back side bump comprising a conductive layer 520 and a capping layer 530.).
Regarding claim 19, Yang teaches a metal pattern disposed between the first back-side metal plate layer and the back-side bump structure, wherein the first back-side metal plate layer extends onto the protruding portion of the through-electrode, and wherein the metal pattern is disposed over the first back-side metal plate layer to be vertically aligned with the through-electrode and the back-side bump structure (Fig. 3 points to an alternative embodiment of a semiconductor chip comprising an interconnection structure 131 (first back-side metal plate layer), an interconnection structure 133 (metal pattern), through via electrodes 270 and bumps 290.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji and Yang, such that a metal pattern is formed between the through-electrode and the back-side bump structure in order to create an interconnection structure that balances electrical isolation and communication between the two components.
Regarding claim 20, Ji in combination with Jung teaches wherein the first back-side metal plate layer is disposed in the dummy region (Fig. 2Z of Ji points to the redistribution layer 400 (first back-side metal plate layer) located directly under the back side bump comprising a conductive layer 520 and a capping layer 530. Fig. 2 of Jung points to the outer area (dummy area) corresponding to dummy bumps 267.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji et al. and Jung, such that the first back-side metal plate layer is disposed over the bump structures located in both the dummy region and through-electrode region in order to improve adhesion and/or physical stability within the dummy region.
Claim(s) 4-5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. in further view of Huang (PGPub No. 20230154764).
Regarding claim 4, Huang teaches wherein the front-side bump structure includes: a front-side UBM (Under Bump Metallurgy) layer; a front-side bump body disposed under a lower surface of the front-side UBM layer; and a solder layer under the lower surface of the front-side bump body above, and wherein the back-side bump structure includes: a back-side UBM layer; a back-side bump body disposed over the back-side UBM layer; and a back-side bump capping layer disposed over the back-side bump body (Fig. 11 point to UBMs 77 (front-side UBM layer; back-side UBM layer) and electrical connectors 78 (front-side bump body; back-side bump body). [0043] further points to alternative embodiments where the formation of the electrical connectors 78 either include performing a plating process to form solder layers or forming non-solder metal pillars and solder caps (back-side bump capping layer) over said pillars.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji et al. and Huang, such that the front-side and back-side bump structures are each formed to include a UBM layer, a bump body, a solder layer, and/or a capping layer in order to establish points of communication with external components/devices such as an independent passive device, a package substrate, or an interposer.
Regarding claim 5, Huang teaches wherein the first back-side metal plate layer include multi layers, wherein the multi layers include: a lower metal layer including titanium: and an upper metal layer including at least one of copper and nickel ([0042] points to the UBMs 77 (first back-side metal plate layer) comprising a titanium layer and a copper layer over the titanium layer.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji et al. and Huang, such that the first back-side metal plate layer comprises a lower layer of titanium and an upper layer of copper in order to make use of the adhesive properties of titanium while also utilizing the electrical conductivity and solder wettability of copper.
Regarding claim 17, Huang teaches wherein the first back-side metal plate layer includes a lower UBM (Under Bump Metallurgy) layer including titanium and an upper UBM layer including at least one of copper and nickel ([0042] points to the UBMs 77 (first back-side metal plate layer) comprising a titanium layer and a copper layer over the titanium layer.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ji et al. and Huang, such that the first back-side metal plate layer comprises a lower layer of titanium and an upper layer of copper in order to make use of the adhesive properties of titanium while also utilizing the electrical conductivity and solder wettability of copper.
Conclusion
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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