Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Embodiment of Figs. 5A-5B (Claims 1-8, 13, 14 and 17-20) in the reply filed on 02/10/2026 is acknowledged.
Claims 9-12 and 15-16 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/10/2026.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/30/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 14 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ganesan et al. (US 2021/0305162).
As claim 1, Ganesan et al. disclose in fig. 3 and the related text a semiconductor package, comprising:
a lower redistribution structure 306 comprising a lower redistribution layer (pad form in 306);
a lower chip structure 100 disposed on the lower redistribution structure and electrically connected to the lower redistribution layer (Fig. 3);
a plurality of posts (211/pad, (similar to pad 607/609, Fig. 6G)) disposed adjacent to the lower chip structure and comprising a lower metal layer (pad) disposed on the lower redistribution layer and an upper metal layer 211 disposed on the lower metal layer (Fig. 3);
an encapsulant 352 covering respective side surfaces of the lower chip structure and the plurality of posts (Fig. 3);
a heat dissipation member 331/333 disposed on the encapsulant and vertically overlapping at least a portion of the lower chip structure (Fig. 3);
an upper chip structure 114-1 disposed on one (lower) side of the heat dissipation member, vertically overlapping at least a portion of the plurality of posts (Fig. 3), and electrically connected to the lower redistribution layer through the plurality of posts (Fig. 3); and a plurality of external connection bumps 354 disposed below the lower redistribution structure 306 and electrically connected to the lower redistribution layer (Fig. 3), wherein the lower metal layer (pad) and the upper metal layer 211 comprise different metals ([0029], [0052]).
As claim 2, Ganesan et al. disclose the semiconductor package of claim 1, wherein the lower metal layer comprises a first metal, and the upper metal layer comprises a second metal having a diffusion coefficient lower than a diffusion coefficient of the first metal in silicon (Ganesan et al teach in [0029], [0052] the lower metal layer and the upper metal layer comprising the same materials of claimed invention, therefore the upper metal layer comprises a second metal having a diffusion coefficient lower than a diffusion coefficient of the first metal in silicon).
As claim 3, Ganesan et al. disclose the semiconductor package of claim 1, wherein a height of the lower metal layer (pad) is about equal to or greater than a height of (a portion of) the upper metal layer 211.
As claim 5, Ganesan et al. disclose the semiconductor package of claim 3, wherein the plurality of posts further comprise a seed layer (lower portion of the pad) disposed between the lower metal layer (pad) and the lower redistribution layer 306, and the height of the upper metal layer 211 is greater than a height of the seed layer (lower portion of the pad).
As claim 6, Ganesan et al. disclose the semiconductor package of claim 1, further comprising: a plurality of lower connection bumps 352 disposed between the lower chip structure 100 and the lower redistribution structure 306; and a plurality of upper connection bumps 250-2 disposed between the upper chip structure 114-1 and the plurality of posts (Fig. 3).
As claim 7, Ganesan et al. disclose the semiconductor package of claim 1, wherein the heat dissipation member 333 comprises a thermal interface material [0039] disposed on the lower chip structure and a heat slug 331 disposed on the thermal interface material (Fig. 3).
As claim 8, Ganesan et al. disclose the semiconductor package of claim 1, wherein the lower chip structure 100 comprises a logic chip [0021], and the upper chip structure 114-1 comprises a memory chip [0067].
As claim 14, Ganesan et al. disclose the semiconductor package of claim 1, wherein the plurality of posts comprise a plurality of dummy posts (right 211/pad) not vertically overlapping the upper chip structure (Fig. 3).
As claim 17, Ganesan et al. disclose in fig. 3 and the related text a semiconductor package, comprising:
a lower redistribution structure 306/pads form in 306;
a lower chip structure 100 disposed on the lower redistribution structure (Fig. 3);
a plurality of posts 211 disposed adjacent to the lower chip structure and comprising a lower metal layer (lower portion of 211) and an upper metal layer (upper portion of 211) disposed on the lower metal layer (Fig. 3);
an encapsulant 352 covering at least portions of the lower chip structure and the plurality of posts (Fig. 3);
a heat dissipation member 331/333 disposed on the encapsulant and vertically overlapping at least a portion of the lower chip structure (Fig. 3);
an upper chip structure 114-1 disposed on one (lower) side of the heat dissipation member and vertically overlapping at least portions of the plurality of posts (Fig. 3); and
a plurality of upper connection bumps 250-2 disposed between the upper chip structure 114-1 and the plurality of posts 211,
wherein a side surface of the lower metal layer (lower portion of 211) and a side surface of the upper metal layer (upper portion of 211) are in contact with the encapsulant (Fig. 3), and an upper surface of the upper metal layer (upper portion of 211) is in contact with the upper connection bumps 250-2 (Fig. 3).
As claim 18, Ganesan et al. disclose the semiconductor package of claim 17, wherein the side surface of the lower metal layer (lower portion of 211) and the side surface of the upper metal layer (upper portion of 211) define a same flat surface (Fig. 3).
As claim 19, Ganesan et al. disclose the semiconductor package of claim 17, wherein the upper surface of the upper metal layer 211 is substantially coplanar with an upper surface of the encapsulant 352 and an upper surface of the lower chip structure 100 (Fig. 333).
As claim 20, Ganesan et al. disclose in fig. 3 and the related text a semiconductor package, comprising:
a lower redistribution structure 306/pads form in 306;
a lower chip structure 100 disposed on the lower redistribution structure (Fig. 3);
a plurality of posts 211 disposed adjacent to the lower chip structure and comprising a lower metal layer (lower portion of 211) and an upper metal layer (upper portion of 211) disposed on the lower metal layer (Fig. 3);
an encapsulant 352 covering at least portions of the lower chip structure and the plurality of posts (Fig. 3);
a heat dissipation member 311/333 disposed on the encapsulant and vertically overlapping at least a portion of the lower chip structure (Fig. 3); and
an upper chip structure 114-1 disposed on one (lower) side of the heat dissipation member 331/333 and vertically overlapping at least portions of the plurality of posts 211, wherein a width of the lower metal layer (lower portion of 211) is substantially equal to a width of the upper metal layer (upper portion of 211) (Fig. 3).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ganesan et al..
As claim 4, Ganesan et al. disclose the semiconductor package of claim 3, except the height of the upper metal layer is about 3 µm or more.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide the height of the upper metal layer is about 3 µm or more, in order to optimize the performance of the device. Futhermore, it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ganesan et al. in view of Chiang et al. (2014/0097532).
As claim 13, Ganesan et al. disclose the semiconductor package of claim 1, except on a plane, the heat dissipation member surrounds at least three surfaces of the upper chip structure.
Figs. 3-4a and the related text on a plane, the heat dissipation member 200 surrounds at least three surfaces of the upper chip structure 300.
Chiang et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ganesan et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Ganesan et al., to include the limitations as taught by Chiang et al., in order to is intended to transfer heat away from other components (Chiang ¶0022).
Conclusion
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811