DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-8, 14 and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sun et al. (US 2022/0270976).
As for claim 1, Sun et al. disclose in Figs. 1-13 and the related text a semiconductor package, comprising:
a lower redistribution structure comprising a lower redistribution layer 106/147 including first redistribution pads 179 and second redistribution pads 125;
a lower chip structure 110 disposed on the first redistribution pads and connected to the first redistribution pads (Fig. 13);
a plurality of posts 175 disposed adjacent to the lower chip structure 110 and respectively on the second redistribution pads 125 (fig. 13), each post comprising a lower metal layer (lower of 175) disposed on a respective one of the second redistribution pads and an upper metal layer (upper of 175) disposed on the lower metal layer (Fig. 13);
an encapsulant 183 covering respective side surfaces of the lower chip structure, the first redistribution pads, the second redistribution pads, and the plurality of posts (Fig. 13);
a heat dissipation member 111 disposed on the encapsulant and vertically overlapping at least a portion of the lower chip structure (Fig. 13);
an upper chip structure 130-1 disposed on one (upper) side of the heat dissipation member 111, vertically overlapping at least a portion of the plurality of posts 175, and connected to the lower redistribution layer through the plurality of posts (Fig. 13); and
a plurality of external connection bumps 106 disposed below the lower redistribution structure and connected to the lower redistribution layer (Fig. 13), wherein the lower metal layer and the upper metal layer comprise different metals (Fig. 13, [0048]), and
a width of one of the second redistribution pad 125, on which one of the plurality of posts 175 is disposed, is greater than a width of the lower metal layer and a width of the upper metal layer of the one of the plurality of posts (Fig. 13).
As for claim 2, Sun et al. disclose the semiconductor package of claim 1, wherein the lower metal layer comprises a first metal (Copper), and the upper metal layer comprises a second metal (Nickle) having a diffusion coefficient lower than a diffusion coefficient of the first metal in silicon [0048].
As for claim 3, Sun et al. disclose the semiconductor package of claim 1, wherein a height of the lower metal layer is about equal to or greater than a height of the upper metal layer (Fig. 13).
5. (Original) The semiconductor package of claim 3, wherein the plurality of posts further comprise a seed layer (upper portion of 125) disposed between the lower metal layer (lower portion of 125) and the lower redistribution layer 106/147, and the height of the upper metal layer is greater than a height of the seed layer (fig. 13).
As for claim 6, Sun et al. disclose the semiconductor package of claim 1, further comprising: a plurality of lower connection bumps (106 under 110) disposed between the lower chip structure and the lower redistribution structure (Fig. 13); and a plurality of upper connection bumps (106 above 111) disposed between the upper chip structure and the plurality of posts (Fig. 13).
As for claim 7, Sun et al. disclose the semiconductor package of claim 1, wherein the heat dissipation member 111 comprises a thermal interface material disposed on the lower chip structure 110 and a heat slug 109 disposed on the thermal interface material (Fig. 13).
As for claim 8, Sun et al. disclose the semiconductor package of claim 1, wherein the lower chip structure comprises a logic chip ([0027], [0083)], and the upper chip structure 130-1 comprises a memory chip [0030].
As for claim 14, Sun et al. disclose the semiconductor package of claim 1, wherein the plurality of posts comprise a plurality of dummy posts (right 175) not vertically overlapping the upper chip structure 130-1.
As for claim 17, Sun et al. disclosed in Figs. 1-13 and the related text a semiconductor package, comprising:
a lower redistribution structure 106/147;
a lower chip structure 110/165/177 disposed on the lower redistribution structure (Fig. 13);
a plurality of posts 175 disposed adjacent to the lower chip structure and comprising a lower metal layer (lower 175) and an upper metal layer (upper 175) disposed on the lower metal layer (fig. 13);
an encapsulant 183 covering at least portions of the lower chip structure and the plurality of posts (Fig. 13);
a heat dissipation member 111 disposed on and being in contact with the encapsulant and the lower chip structure (Fig. 13), the heat dissipation member vertically overlapping at least a portion of the lower chip structure (Fig. 13);
an upper chip structure 130-1 disposed on one (upper) side of the heat dissipation member and vertically overlapping at least portions of the plurality of posts (Fig. 13); and
a plurality of upper connection bumps 106 disposed between the upper chip structure and the plurality of posts (Fig. 13), wherein a side surface of the lower metal layer and a side surface of the upper metal layer are in contact with the encapsulant (Fig. 13), and an upper surface of the upper metal layer is in (electrically/thermally) contact with the upper connection bumps 106 (Fig. 13).
As for claim 18, Sun et al. disclose the semiconductor package of claim 17, wherein the (right) side surface of the lower metal layer and the (right) side surface of the upper metal layer define a same flat surface (Fig. 13).
As for claim 19, Sun et al. disclose the semiconductor package of claim 17, wherein the upper surface of the upper metal layer (upper 175) is substantially coplanar with an upper surface of the encapsulant 83 and an upper surface of the lower chip structure 110/165/177 (Fig. 13).
As for claim 20, Sun et al. disclosed in Figs. 1-13 and the related text a semiconductor package, comprising:
a lower redistribution structure 106/147;
a lower chip structure 110/165/177 disposed on the lower redistribution structure (Fig. 13);
a plurality of posts 175 disposed adjacent to the lower chip structure and comprising a lower metal layer (lower 175) and an upper metal layer (upper 175) disposed on the lower metal layer and including a material different from the lower metal layer (Fig. 13, [0048]);
an encapsulant 83 covering at least portions of the lower chip structure and the plurality of posts (Fig. 13);
a heat dissipation member 111 disposed on the encapsulant and vertically overlapping at least a portion of the lower chip structure (fig. 13); and
an upper chip structure 130-1 disposed on one (upper) side of the heat dissipation member and vertically overlapping at least portions of the plurality of posts 175 (Fig. 13), wherein a width of (a portion of) the lower metal layer is substantially equal to a width of the upper metal layer (Fig. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sun et al..
As for claim 4, Sun et al. disclose the semiconductor package of claim 3, except the height of the upper metal layer is about 3 pm or more.
It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the height of the upper metal layer is about 3 pm or more, in order to optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: “on a plane, the heat dissipation member surrounds at least three surfaces of the upper chip structure”, as recited claim 13.
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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