DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on October 30, 2023 and February 26, 2026 are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Light Emitting Display Apparatus Having Reduced Signal Line Parasitic Capacitance.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on November 30, 2023.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-8, and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Min (KR-20220030884-A).
Claim 1, Min discloses a light emitting display apparatus (display device 200 is a light emitting display apparatus, hereinafter, light emitting display apparatus 200, [0105], Figs. 3 and 6), comprising:
a plurality of pixels (plurality of pixels PX, [0109], Figs. 3 and 6), each including a plurality of subpixels (each plurality of pixels PX includes a plurality of subpixels R/G/B/W, [0107], Figs. 3 and 6);
a plurality of data lines (plurality of data wires DL1/DL2/DL3/DL4 is equivalent to a plurality of data lines, hereinafter, plurality of data lines DL1/DL2/DL3/DL4, [0057], Figs. 3 and 6) respectively connected with the respective plurality of subpixels R/G/B/W (plurality of data lines DL1/DL2/DL3/DL4 is respectively connected with the plurality of subpixels R/G/B/W, [0057], Figs. 3 and 6); and
a plurality of reference lines (plurality of reference voltage wires RVL1/RVL2 is equivalent to plurality of reference lines, hereinafter, plurality of reference lines RVL1/RVL2, [0076], Figs. 3 and 6) in each of the plurality of pixels PX (a plurality of reference lines RVL1/RVL2 can be placed in the plurality of pixels PX, [0076], Figs. 3 and 6),
wherein each of the plurality of subpixels R/G/B/W comprises:
a pixel circuit (driving circuit for one sub-pixel SP is a pixel circuit within each of the plurality of subpixels R/G/B/W, hereinafter, pixel circuit SP, [0036], Figs. 2-3 and 6) connected with a corresponding data line (each pixel circuit SP is connected with a corresponding data line DL, [0039], Figs. 2-3 and 6) and a corresponding reference line and a corresponding reference line (each pixel circuit SP is connected with a corresponding reference voltage wiring RVL, hereinafter, reference line RVL, [0039], Figs. 2-3 and 6); and
a light emitting device layer (light-emitting element 150 may be an anode, an organic layer, and a cathode and consists of a light emitting device layer, hereinafter, light emitting device layer 150, [0038], Fig. 2) connected with the pixel circuit SP (light emitting device layer 150 is connected with the pixel circuit SP, [0038], Fig. 2),
a first subpixel group (within the odd-numbered row odd is a first subpixel group comprising the green subpixel G (i.e. 8k-4 column, odd row), red subpixel R (i.e. 8k-7 column, odd row), white subpixel W (i.e. 8k-6 column, odd row), and blue subpixel B (i.e. 8k-5 column, odd row), hereinafter, first subpixel group 8k-7/6/5/4/odd, [0056], Figs. 3 and 6) among the plurality of subpixels R/G/B/W in each of the plurality of pixels PX being connected with a first reference line RVL1 (first subpixel group 8k-7/6/5/4/odd among the plurality of subpixels R/G/B/W in each of the plurality of pixels PX is connected with a first reference line RVL1, [0077], Annotated Fig. 3), and
a second subpixel group (within the odd-numbered row odd is a second subpixel group comprising the green subpixel G (i.e. 8k column, odd row), red subpixel R (i.e. 8k-3 column, odd row), white subpixel W (i.e. 8k-2 column, odd row), and blue subpixel B (i.e. 8k-1 column, odd row), hereinafter, second subpixel group 8k-3/2/1/0/odd, [0066], Annotated Fig. 3) different from the first subpixel group 8k-7/6/5/4/odd among the plurality of subpixels R/G/B/W in each of the plurality of pixels PX being connected with second reference line RVL2 connected with an adjacent different pixel (second subpixel group 8k-3/2/1/0/odd among the plurality of subpixels R/G/B/W in each of the plurality of pixels PX is connected with a second reference line RVL2 connected with an adjacent different pixel, [0078], Annotated Fig. 3).
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Annotated Fig. 3 (Min) – Illustrates a first subpixel group 8k-7/6/5/4/odd comprising the green subpixel G (i.e. 8k-4 column, odd row), red subpixel R (i.e. 8k-7 column, odd row), white subpixel W (i.e. 8k-6 column, odd row), and blue subpixel B (i.e. 8k-5 column, odd row) is connected with first reference line RVL1, and a second subpixel group 8k-3/2/1/0/odd comprising the green subpixel G (i.e. 8k column, odd row), red subpixel R (i.e. 8k-3 column, odd row), white subpixel W (i.e. 8k-2 column, odd row), and blue subpixel B (i.e. 8k-1 column, odd row) is connected with second reference line RVL2 connected with an adjacent different pixel.
Claim 2, Min discloses a light emitting display apparatus (light emitting display apparatus 200, [0105], Figs. 3 and 6) of claim 1, wherein each of the plurality of pixels PX further comprises:
a first connection line (odd-numbered gate wiring GL1 is a first connection line, hereinafter, first connection line GL1, [0110]. Annotated Fig. 3) connected between a subpixel R/G/B/W of the first subpixel group 8k-7/6/5/4/odd (first connection line GL1 is connected between a subpixel R/G/B/W of the first subpixel group 8k-7/6/5/4/odd, [0111], Annotated Fig. 3) and the corresponding reference line RVL1 (first connection line GL1 is connected between a subpixel R/G/B/W of the first subpixel group 8k-7/6/5/4/odd and the corresponding reference line RVL1, [0085], Fig. 2 and Annotated Fig. 3); and
a second connection line (even-numbered gate wiring GL2 is a second connection line, hereinafter, second connection line GL2, [0082]. Annotated Fig. 3) connected between a subpixel R/G/B/W of the second subpixel group 8k-3/2/1/0/odd (second connection line GL2 is connected between a subpixel R/G/B/W of the second subpixel group 8k-3/2/1/0/odd, [0111], Fig. 6 and Annotated Fig. 3) and the second reference line RVL2 in the adjacent different pixel (second connection line GL2 is connected between a subpixel R/G/B/W of the second subpixel group 8k-3/2/1/0/odd and the second reference line RVL2 in the adjacent different pixel, [0111], Fig. 6 and Annotated Fig. 3).
Claim 5, Min discloses a light emitting display apparatus (light emitting display apparatus 200, [0105], Figs. 3 and 6) of claim 2, wherein the plurality of data lines DL1/DL2/DL3/DL4 are at each of a left side and a right side of the respective reference line RVL1/RVL2 with the respective reference line RVL1/RVL2 therebetween (plurality of data lines DL1/DL2/DL3/DL4 are at each of a left side and a right side of the respective reference line RVL1/RVL2 with the respective reference line RVL1/RVL2 therebetween, Annotated Fig. 3).
Claim 6, Min discloses a light emitting display apparatus (light emitting display apparatus 200, [0105], Figs. 3 and 6) of claim 5, wherein one of the plurality of data lines DL1/DL2/DL3/DL4 at each of the left side and the right side does not overlap all of the first connection line GL1 and the second connection line GL2 (one of the plurality of data lines DL1/DL2/DL3/DL4 at each of the left side and the right side does not overlap all of the first connection line GL1 and the second connection line GL2, Annotated Fig. 3).
Claim 7, Min discloses a light emitting display apparatus (light emitting display apparatus 200, [0105], Figs. 3 and 6) of claim 2, further comprising a driving power line (high-potential voltage line VDDL is a driving power line, hereinafter, driving power line VDDL, [0040], Fig. 2 and Annotated Fig. 6) provided in each of the plurality of pixels PX (driving power line VDDL is provided in each of the plurality of pixels PX, [0040], Fig. 2 and Annotated Fig. 6).
Claim 8, Min discloses a light emitting display apparatus (light emitting display apparatus 200, [0105], Figs. 3 and 6) of claim 7, wherein the driving power line VDDL overlaps the second connection line GL2 (driving power line VDDL overlaps the second connection line GL2, Fig. 2 and Annotated Fig. 3).
Claim 21, Min discloses a light emitting display apparatus (display device 200 is a light emitting display apparatus, hereinafter, light emitting display apparatus 200, [0105], Figs. 3 and 6), comprising:
a plurality of pixels (plurality of pixels PX, [0109], Figs. 3 and 6), each including a plurality of subpixels (each plurality of pixels PX includes a plurality of subpixels R/G/B/W, [0107], Figs. 3 and 6), wherein the plurality of subpixels R/G/B/W includes a green subpixel (fourth sub-pixel G is a green subpixel, hereinafter, green subpixel G, [0060], Figs. 3 and 6), a red subpixel (first sub-pixel R is a red subpixel, hereinafter, red subpixel R, [0060], Figs. 3 and 6), a white subpixel (second sub-pixel W is a white subpixel, hereinafter, white subpixel W, [0061], Figs. 3 and 6) and a blue subpixel (third sub-pixel B is a blue subpixel, hereinafter, blue subpixel B, [0063], Figs. 3 and 6);
a plurality of data lines (plurality of data wires DL1/DL2/DL3/DL4 is equivalent to a plurality of data lines, hereinafter, plurality of data lines DL1/DL2/DL3/DL4, [0057], Figs. 3 and 6) respectively connected with the plurality of subpixels R/G/B/W (plurality of data lines DL1/DL2/DL3/DL4 is respectively connected with the plurality of subpixels R/G/B/W, [0057], Figs. 3 and 6); and
a plurality of reference lines (plurality of reference voltage wires RVL1/RVL2 is equivalent to plurality of reference lines, hereinafter, plurality of reference lines RVL1/RVL2, [0076], Figs. 3 and 6) in each of the plurality of pixels PX (a plurality of reference lines RVL1/RVL2 can be placed in the plurality of pixels PX, [0076], Figs. 3 and 6),
wherein each of the plurality of subpixels R/G/B/W includes a pixel circuit (driving circuit for one sub-pixel SP is a pixel circuit within each of the plurality of subpixels R/G/B/W, hereinafter, pixel circuit SP, [0036], Figs. 2-3 and 6) connected with a corresponding data line (each pixel circuit SP is connected with a corresponding data line DL, [0039], Figs. 2-3 and 6) of the plurality of data lines DL1/DL2/DL3/DL4 (each pixel circuit SP is connected with a corresponding data line DL of the plurality of data lines DL1/DL2/DL3/DL4, [0039], Figs. 2-3 and 6) and a corresponding reference line (each pixel circuit SP is connected with a corresponding reference voltage wiring RVL, hereinafter, reference line RVL, [0039], Figs. 2-3 and 6) of the plurality of reference lines RVL1/RVL2 (each pixel circuit SP is connected with a corresponding reference line RVL of the plurality of reference lines RVL1/RVL2, [0039], Figs. 2-3 and 6),
wherein a first subpixel group (within the odd-numbered row odd is a first subpixel group comprising the green subpixel G (i.e. 8k-4 column, odd row), red subpixel R (i.e. 8k-7 column, odd row), white subpixel W (i.e. 8k-6 column, odd row), and blue subpixel B (i.e. 8k-5 column, odd row), hereinafter, first subpixel group 8k-7/6/5/4/odd, [0056], Figs. 3 and 6) among the plurality of subpixels R/G/B/W in each of the plurality of pixels PX is connected with a first reference line RVL1 (first subpixel group 8k-7/6/5/4/odd among the plurality of subpixels R/G/B/W in each of the plurality of pixels PX is connected with a first reference line RVL1, [0077], Annotated Fig. 3), wherein the first subpixel group 8k-7/6/5/4/odd includes the green subpixel G, the red subpixel R and the white subpixel W (first subpixel group 8k-7/6/5/4/odd includes the green subpixel G, the red subpixel R and the white subpixel W, [0077], Annotated Fig. 3), and
wherein a second subpixel group (within the odd-numbered row odd is a second subpixel group comprising the green subpixel G (i.e. 8k column, odd row), red subpixel R (i.e. 8k-3 column, odd row), white subpixel W (i.e. 8k-2 column, odd row), and blue subpixel B (i.e. 8k-1 column, odd row), hereinafter, second subpixel group 8k-3/2/1/0/odd, [0066], Annotated Fig. 3) except the first subpixel group 8k-7/6/5/4/odd among the plurality of subpixels R/G/B/W in each of the plurality of pixels PX is connected with second reference line RVL2 connected with an adjacent different pixel (second subpixel group 8k-3/2/1/0/odd among the plurality of subpixels R/G/B/W in each of the plurality of pixels PX is connected with a second reference line RVL2 connected with an adjacent different pixel, [0078], Annotated Fig. 3), wherein the second subpixel group 8k-3/2/1/0/odd includes the blue subpixel B (second subpixel group 8k-3/2/1/0/odd includes the blue subpixel B, [0078], Annotated Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Jang (US 2022/0037440 A1).
Claim 9, Min discloses a light emitting display apparatus (light emitting display apparatus 200, [0105], Figs. 3 and 6) of claim 2,
Min does not explicitly disclose wherein the first connection line GL1 and the second connection line GL2 are provided on the same layer as the first reference line RVL1.
However, Jang discloses wherein the connection line GL is provided on the same layer as the reference line VREFH, (Jang, gate line GL is a connection line for the subpixel group and is provided on the same layer as the reference line VREFH, [0111], Fig. 15; Min, Annotated Fig. 3). The combination to deposit both lines on the same layer allow for the material to be the same (Jang, [0112]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to deposit both lines on the same layer allow for the material to be the same (Jang, [0112]).
Claim 10, Min/Jang discloses the light emitting display apparatus (Min, light emitting display apparatus 200, [0105], Annotated Fig. 3; Jang, Fig. 15) of claim 9, wherein the connection line GL comprise the same material as a material of the reference line VREFH (Jang, connection line GL comprise the same material as a material of the reference line VREFH, [0112], Fig. 15; Min, Annotated Fig. 3).
Claim 11, Min discloses a light emitting display apparatus (light emitting display apparatus 200, [0105], Figs. 3 and 6) of claim 2.
Min does not explicitly disclose further comprising an insulation layer provided between the first and second connection lines and the plurality of data lines.
However, Jang discloses further comprising an insulation layer provided between the connection line GL (connection line GL is formed on an inter-layer dielectric ILD film, which is an insulation layer, hereinafter, insulation layer ILD, [0103], Fig. 12) and the plurality of data lines DL (Jang, connection line GL is formed on insulation layer ILD, and data lines DL are formed on the substrate SUB as the light-shielding layer LS, [0103], Fig. 12; Min, Annotated Fig. 3). The combination to dispose an insulation layer between the connection line and data lines to properly isolate independent sources of electrical interference and to cover the underlying conductive material (Jang, [0110], Fig. 14; Min, Annotated Fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to dispose an insulation layer between the connection line and data lines to properly isolate independent sources of electrical interference and to cover the underlying conductive material (Jang, [0110], Fig. 14; Min, Annotated Fig. 3).
Allowable Subject Matter
Claim(s) 3-4 and 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Min (KR-20220030884-A), Jang (US 2022/0037440 A1), fails to disclose the following limitations in combination with the rest of the claim.
Regarding claim 3, the second connection line does not overlap the data line.
Min discloses a light emitting display apparatus (light emitting display apparatus 200, [0105], Figs. 3 and 6) of claim 2, wherein, in each of the plurality of pixels PX, the first connection line GL1 overlaps a portion of the data line DL (each of the plurality of pixels PX, the first connection line GL1 overlaps a portion of the data line DL1/DL2/DL3/DL4, [0057], Annotated Fig. 3).
Min does not explicitly disclose the following limitation; the second connection line does not overlap the data line.
Regarding claim 4 (from which claims 12-13 depend), wherein a first pixel and a last pixel of the plurality of pixels, arranged in a second direction perpendicular to a first direction which is a length direction of the reference line, are dummy pixels.
Regarding claim 14 (from which claims 15-20 depend), further comprising a third connection line connecting a first set of second connection lines, provided in each of the plurality of pixels, with each other.
Conclusion
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812