DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, direct to Claims 21-27, and 35-40 in the reply filed on 03/23/2026 is acknowledged and is under consideration.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 09/19/2025 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The previously presented claims 15-27, and 35-40 filed on 03/23/2026 have been fully considered for examination based on their merits. The claims 28-34 have been withdrawn by the Applicant. Claims 1-20 are canceled.
Response to Arguments
Applicant elected (see Remarks, pages 6-7, filed 03/23/2026), Invention I, including previously presented (or original) claims, 15-27, and 35-40, are considered for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-27, and 35-40 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by David S. Pratt et al, (hereinafter PRATT), US 20090166846 A1.
Regarding Claim 21, PRATT teaches a system (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) comprising:
a first semiconductor die (Figs. 1A/7, 20/22/620, first die/substrate); and
a second semiconductor die (Figs. 1A/7, 62/660, second die substrate) stacked vertically (annotated Figure 1A) on the first semiconductor die (Figs. 1A, 20/22/620, first die/substrate);
wherein the first semiconductor die (Figs. 1A, 20/22/620, first die/substrate) includes a first interface (Figs. 6A/7, 550a/550b/655a/655b, first/second 3D/conventional interconnect/, [0034]) and a second interface configured to convey one or more signals (Figs. 6B/7, 544a, metal OLB pad to the interconnect, 550a/550b, [0035]) to the second semiconductor die (Fig. 1A/7, 62/660, second die substrate) stacked vertically (annotated Figure 1A);
wherein the second semiconductor die (Figs. 1A/7, 62/660, second die substrate) comprises an insulated portion (Figs. 4/7, 14, 346/348, insulating layers, [0032]) aligned with at least one of the first interface (Figs. 6A/7, 550a/550b/655a/655b, first/second 3D/conventional interconnect/, [0034]) and the second interface (Figs. 6B/7, 544a, metal OLB pad to the interconnect, 550a/550b, [0035]) that prevents the one or more signals from being used by the second semiconductor die (without also communicating this signal to the second memory device, 674, [0036]) at the at least one of the first interface (Fig. 6A, 550a/550b, first 3D interconnect, [0034]) and second interface (Fig. 6B, 544a/544b, metal OLD pad to the interconnect, 550a/550b, [0035]).
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Regarding Claim 22, PRATT teaches the system in package (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) as recited in claim 21, wherein an active device layer (Fig. 7, 634, first memory device), of the first semiconductor die (Fig. 7, 620, first die) is stacked vertically on top (annotated Figure 7) of an active device layer (Fig. 7, 674, second memory device) of the second semiconductor die (Fig. 7, 660, second die), wherein each active device layer (Fig. 7, 634/674, first/second memory device) comprises a vertical interconnect (Fig. 7, 650/655a/655b, pass-through interconnect/first/second conventional 3D interconnects) traversing through (annotated Figure 7) the active device layer (Fig. 7, 634/674, first/second memory device).
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Regarding Claim 23, PRATT teaches the system in package (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) as recited in claim 22, wherein silicon vias (Fig. 7, through-silicon vias, [0014]) corresponding to vertical interconnects (Fig. 7, 650/655a/655b, pass-through interconnect/first/second conventional 3D interconnects) are grouped together to form through silicon buses (Fig. 7, through-die or through-silicon vias, [0014]).
Regarding Claim 24, PRATT teaches the system in package (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) as recited in claim 21, wherein the first semiconductor die (annotated Figure 3H) includes a through silicon via (Figs. 3F/3H, 223/227, second holes) that does not fully traverse (annotated Figure 3H) the first semiconductor die (annotated Figure 3H).
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Regarding Claim 25, PRATT teaches the system in package (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) as recited in claim 24, wherein the first semiconductor die (Fig. 7, 620, first die) includes one or more metal layers (Figs. 6A-6B/7, 582/582b/542a/542b, metal trace) located above the through silicon via (annotated Figure 6A), wherein each metal layer (Figs. 6A-6B/7, 582/582b/542a/542b, metal trace) connects to one of the first interface (Figs. 6A/7, 550a/550b/655a/655b, first/second 3D/conventional interconnect/, [0034]) and the second interface (Figs. 6B/7, 544a, metal OLB pad to the interconnect, 550a/550b, [0035]).
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Regarding Claim 26, PRATT teaches the system in package (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) as recited in claim 25, wherein the second semiconductor die (Fig. 7, 660, second die) comprises a through silicon via aligned (annotated Figure 7) with one of the first interface (Figs. 6A/7, 550a/550b/655a/655b, first/second 3D/conventional interconnect/, [0034]) and the second interface (Figs. 6B/annotated Figure 7, 544a, metal OLB pad to the interconnect, 550a/550b, [0035]), when one or more signals transferred using the through silicon via of the first semiconductor die are to be shared with the second semiconductor die (Figs. 6A/6B, the interconnect, 550b, may concurrently communicate a signal to the integrated circuit, 534, and to another integrated circuit, 574, not shown) electrically coupled with the trace, 582b, [0034]).
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Regarding Claim 27, PRATT teaches the system in package (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) as recited in claim 25, wherein one of the first interface (Figs. 6A/7, 550a/550b/655a/655b, first/second 3D/conventional interconnect/, [0034]) or the second interface (Figs. 6B/7, 544a, metal OLB pad to the interconnect, 550a/550b, [0035]) is a bonding pad interface (Fig. 6B, 544a, metal OLB (outer lead bond) pad, [0015], [0035]) that connects (annotated Figure 6A) to each of the one or more metal layers (Figs. 6A/6B, 542a/542b/582a/582b, metal trace) through a bonding pad via (annotated Figure 6A; through-die, or through-silicon vias, [0014]).
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Regarding Claim 35, PRATT teaches a system in package (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) comprising:
a first semiconductor die (Figs. 1A/7, 20/22/620, first die/substrate) comprising a first interface (Figs. 6A/7, 550a/550b/655a/655b, first/second 3D/conventional interconnect/, [0034]) and a second interface configured to convey one or more signals (Figs. 6B/7, 544a, metal OLB pad to the interconnect, 550a/550b, [0035]); and
a second semiconductor die (Figs. 1A/7, 62/660, second die substrate) comprising an insulated portion (Figs. 4/7, 14, 346/348, insulating layers, [0032]) aligned with at least one of the first interface (Figs. 6A/7, 550a/550b/655a/655b, first/second 3D/conventional interconnect/, [0034]) and the second interface (Figs. 6B/7, 544a, metal OLB pad to the interconnect, 550a/550b, [0035]) that prevents the one or more signals from being used by the second semiconductor die (without also communicating this signal to the second memory device, 674, [0036]) at the at least one of the first interface (Fig. 6A, 550a/550b, first 3D interconnect, [0034]) and second interface (Fig. 6B, 544a/544b, metal OLD pad to the interconnect, 550a/550b, [0035]).
Regarding Claim 36, PRATT teaches a system (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) as recited in claim 35, wherein an active device layer (Fig. 7, 634, first memory device), of the first semiconductor die (Fig. 7, 620, first die) is stacked vertically on top (annotated Figure 7) of an active device layer (Fig. 7, 674, second memory device) of the second semiconductor die (Fig. 7, 660, second die), wherein each active device layer (Fig. 7, 634/674, first/second memory device) comprises a vertical interconnect (Fig. 7, 650/655a/655b, pass-through interconnect/first/second conventional 3D interconnects) traversing through (annotated Figure 7) the active device layer (Fig. 7, 634/674, first/second memory device).
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Regarding Claim 37, PRATT teaches the system (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) as recited in claim 36, wherein silicon vias (Fig. 7, through-silicon vias, [0014]) corresponding to vertical interconnects (Fig. 7, 650/655a/655b, pass-through interconnect/first/second conventional 3D interconnects) are grouped together to form through silicon buses (Fig. 7, through-die or through-silicon vias, [0014]).
Regarding Claim 38, PRATT teaches the system (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) as recited in claim 35, wherein the first semiconductor die (annotated Figure 3H) includes a through silicon via (Figs. 3F/3H, 223/227, second holes) that does not fully traverse (annotated Figure 3H) the first semiconductor die (annotated Figure 3H).
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Regarding Claim 39, PRATT teaches the system (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) as recited in claim 38, wherein the first semiconductor die (Fig. 7, 620, first die) includes one or more metal layers (Figs. 6A-6B/7, 582/582b/542a/542b, metal trace) located above the through silicon via (annotated Figure 6A), wherein each metal layer (Figs. 6A-6B/7, 582/582b/542a/542b, metal trace) connects to one of the first interface (Figs. 6A/7, 550a/550b/655a/655b, first/second 3D/conventional interconnect/, [0034]) and the second interface (Figs. 6B/7, 544a, metal OLB pad to the interconnect, 550a/550b, [0035]).
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Regarding Claim 40, PRATT teaches the system in package (Figs. 1A/7, 10600, system of stacked microelectronic dies/memory system, [0004]) as recited in claim 39, wherein the second semiconductor die (Fig. 7, 660, second die) comprises a through silicon via aligned (annotated Figure 7) with one of the first interface (Figs. 6A/7, 550a/550b/655a/655b, first/second 3D/conventional interconnect/, [0034]) and the second interface (Figs. 6B/annotated Figure 7, 544a, metal OLB pad to the interconnect, 550a/550b, [0035]), when one or more signals transferred using the through silicon via of the first semiconductor die are to be shared with the second semiconductor die (Figs. 6A/6B, the interconnect, 550b, may concurrently communicate a signal to the integrated circuit, 534, and to another integrated circuit, 574, not shown) electrically coupled with the trace, 582b, [0034]).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20170301657 A1 – Figure 1
STATEMENT OF RELEVANCE – Schematic view of a two-device 3D stacking process.
US 20170365600 A1 – Figure 4
STATEMENT OF RELEVANCE – A cross-sectional view of the monolithic 3D IC.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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